# US 2014/0195774 A1 · Apparatus and method for sliding window data access

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- Number: US 2014/0195774 A1
- Document ID: US20140195774A1
- Status: Published application
- Kind: A1
- Application number: 13/995,793
- Filed: 2011-12-22
- Published: 2014-07-10
- Earliest claimed: 2011-12-22
- Assignees: Intel Corporation
- Inventors: Ashish Jha
- Web page: https://patentgrep.com/patent/US20140195774A1

## CPC

- G06F 9/3013: {according to data content, e.g. floating-point registers, address registers}
- G06F 8/76: Adapting program code to run in a different environment; Porting
- G06F 9/30014: {with variable precision}
- G06F 9/30018: {Bit or string instructions}
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/30038: {using a mask}
- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/30047: {Prefetch instructions; cache control instructions}
- G06F 9/30127: {Register windows}
- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/30185: {according to one or more bits in the instruction, e.g. prefix, sub-opcode}
- G06F 9/345: of multiple operands or results {(addressing multiple banks G06F12/06)}
- G06F 9/3555: {using scaling, e.g. multiplication of index}
- G06F 9/383: {Operand prefetching (cache prefetching G06F12/0862)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An apparatus and method are described for fetching and storing a plurality of portions of a data stream into a plurality of registers. For example, a method according to one embodiment includes the following operations: determining a set of N vector registers into which to read N designated portions of a data stream stored in system memory; determining the system memory addresses for each of the N designated portions of the data stream; fetching the N designated portions of the data stream from the system memory at the system memory addresses; and storing the N designated portions of the data stream into the N vector registers.

## Claims

### Claim 1

A processor to execute an instruction to perform the operations of:
determining a set of N vector registers into which to read N designated portions of a data stream stored in system memory;
determining the system memory addresses for each of the N designated portions of the data stream;
fetching the N designated portions of the data stream from the system memory at the system memory addresses; and
storing the N designated portions of the data stream into the N vector registers.

### Claim 2 (depends on 1)

The processor as in claim 1 wherein determining the system memory addresses comprises directly determining a first system memory address from the instruction and calculating the remaining N−1 addresses by adding multiples of a slide value to the first system memory address.

### Claim 3 (depends on 2)

The processor as in claim 2 wherein the slide value is set to be equal to a size of a data element of the data stream.

### Claim 4 (depends on 1)

The processor as in claim 1 wherein the portions of the data stream comprise data elements of the data stream.

### Claim 5 (depends on 1)

The processor as in claim 1 wherein the instruction is specified in the form INSTRUCTION REG1, COUNT, MEMLOCATION, where REG1 comprises a first vector register to store a first portion of a data stream, COUNT comprises the number of portions of the data stream to be fetched from the system memory, and MEMLOCATION comprises the memory location for the first portion of the data stream.

### Claim 6 (depends on 5)

The processor as in claim 5 wherein COUNT is set to a value of 16 for 16 portions of the data stream.

### Claim 7 (depends on 1)

The processor as in claim 1 wherein each of the N portions of the data stream comprise floating point values and wherein each of the N vector registers comprise floating point registers.

### Claim 8 (depends on 7)

The processor as in claim 7 wherein each of the floating point values comprise scalar floating point values.

### Claim 9 (depends on 7)

The processor as in claim 7 wherein each of the floating point values comprise double floating point values.

### Claim 10 (depends on 1)

The processor as in claim 1 wherein each of the N portions of the data stream comprise integer values.

### Claim 11 (depends on 10)

The processor as in claim 10 wherein each of the integer values comprise packed doubleword values.

### Claim 12 (depends on 10)

The processor as in claim 10 wherein each of the integer fvalues comprise packed quadword values.

### Claim 13

A method comprising:
determining a set of N vector registers into which to read N designated portions of a data stream stored in system memory;
determining the system memory addresses for each of the N designated portions of the data stream;
fetching the N designated portions of the data stream from the system memory at the system memory addresses; and
storing the N designated portions of the data stream into the N vector registers.

### Claim 14 (depends on 13)

The method as in claim 13 wherein determining the system memory addresses comprises directly determining a first system memory address from the instruction and calculating the remaining N−1 addresses by adding multiples of a slide value to the first system memory address.

### Claim 15 (depends on 14)

The method as in claim 14 wherein the slide value is set to be equal to a size of a data element of the data stream.

### Claim 16 (depends on 13)

The method as in claim 13 wherein the portions of the data stream comprise data elements of the data stream.

### Claim 17 (depends on 13)

The method as in claim 13 wherein the instruction is specified in the form INSTRUCTION REG1, COUNT, MEMLOCATION, where REG1 comprises a first vector register to store a first portion of a data stream, COUNT comprises the number of portions of the data stream to be fetched from the system memory, and MEMLOCATION comprises the memory location for the first portion of the data stream.

### Claim 18 (depends on 17)

The method as in claim 17 wherein COUNT is set to a value of 16 for 16 portions of the data stream.

### Claim 19 (depends on 13)

The method as in claim 13 wherein each of the N portions of the data stream comprise floating point values and wherein each of the N vector registers comprise floating point registers.

### Claim 20 (depends on 19)

The method as in claim 19 wherein each of the floating point values comprise scalar floating point values.

### Claim 21 (depends on 19)

The method as in claim 19 wherein each of the floating point values comprise double floating point values.

### Claim 22 (depends on 13)

The method as in claim 13 wherein each of the N portions of the data stream comprise integer values.

### Claim 23 (depends on 22)

The method as in claim 22 wherein each of the integer values comprise packed doubleword values.

### Claim 24 (depends on 22)

The method as in claim 22 wherein each of the integer fvalues comprise packed quadword values.

### Claim 25

A computer system comprising:
a memory for storing program instructions and data;
a processor to execute one or more of the program instructions to perform the operations of:
determining a set of N vector registers into which to read N designated portions of a data stream stored in system memory;
determining the system memory addresses for each of the N designated portions of the data stream;
fetching the N designated portions of the data stream from the system memory at the system memory addresses; and
storing the N designated portions of the data stream into the N vector registers.

### Claim 26 (depends on 25)

The system as in claim 25 further comprising:
a display adapter to render graphics images in response to execution of the program code by the processor.

### Claim 27 (depends on 26)

The system as in claim 26 further comprising:
a user input interface to receive control signals from a user input device, the processor executing the program code in response to the control signals.

### Claim 28

A processor to execute an instruction comprising:
means for determining a set of N vector registers into which to read N designated portions of a data stream stored in system memory;
means for determining the system memory addresses for each of the N designated portions of the data stream;
means for fetching the N designated portions of the data stream from the system memory at the system memory addresses; and
means for storing the N designated portions of the data stream into the N vector registers.

### Claim 29 (depends on 28)

The processor as in claim 28 wherein means for determining the system memory addresses comprises directly determining a first system memory address from the instruction and calculating the remaining N−1 addresses by adding multiples of a slide value to the first system memory address.

### Claim 30 (depends on 29)

The processor as in claim 29 wherein the slide value is set to be equal to a size of a data element of the data stream.

### Claim at position 31

-39. (canceled)