# US 2014/0195772 A1 · System and method for out-of-order prefetch instructions in an in-order pipeline > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0195772 A1 - Document ID: US20140195772A1 - Status: Published application - Kind: A1 - Application number: 13/995,907 - Filed: 2011-12-20 - Published: 2014-07-10 - Earliest claimed: 2011-12-20 - Assignees: Intel Corporation - Inventors: James Earl McCormick, JR. - Web page: https://patentgrep.com/patent/US20140195772A1 ## CPC - G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] - G06F 9/30047: {Prefetch instructions; cache control instructions} - G06F 9/383: {Operand prefetching (cache prefetching G06F12/0862)} - G06F 12/0862: with prefetch - G06F 12/1009: using page tables, e.g. page table structures - G06F 2212/654: Look-ahead translation - G06F 2212/684: TLB miss handling - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Apparatuses, systems, and a method for providing a processor architecture with data prefetching are described. In one embodiment, a system includes one or more processing units that include a first type of in-order pipeline to receive at least one data prefetch instruction. The one or more processing units include a second type of in-order pipeline having issues slots to receive instructions and a data prefetch queue to receive the at least one data prefetch instruction. The data prefetch queue may issue the at least one data prefetch instruction to the second type of in-order pipeline based upon one or more factors (e.g., at least one execution slot of the second type of in-order pipeline being available, priority of the data prefetch instruction). ## Claims ### Claim 1 A processor architecture, comprising: at least one in-order pipeline to receive data prefetch instructions and other instructions; a translation lookaside buffer (TLB) with a number of ports for mapping virtual addresses to physical addresses; a data prefetch queue to receive data prefetch instructions when a respective virtual address associated with a respective data prefetch instruction is not found in the TLB; and a hardware page walker to access page tables in memory when respective data prefetch instructions are not found in the TLB. ### Claim 2 (depends on 1) The processor architecture of claim 1, wherein the at least one in-order pipeline is an arithmetic logic unit (ALU) pipeline to receive ALU instructions and data prefetch instructions. ### Claim 3 (depends on 1) The processor architecture of claim 1, further comprising: at least one of a second type of in-order pipeline having issues slots to receive a plurality of other instructions. ### Claim 4 (depends on 3) The processor architecture of claim 3, wherein the data prefetch queue to issue data prefetch instructions to the at least one of the second type of in-order pipeline upon at least one execution slot of the at least one of the second type of in-order pipeline being available. ### Claim 5 (depends on 1) The processor architecture of claim 1, wherein multiple hardware page walks are coalesced into a single page walk when multiple instructions concurrently request the same translation from the hardware page walker. ### Claim 6 (depends on 1) The processor architecture of claim 1, wherein the at least one in-order pipeline is an integer pipeline to receive integer instructions and data prefetch instructions. ### Claim 7 (depends on 1) The processor architecture of claim 1, wherein the at least one of the second type of in-order pipeline execute while multiple hardware page walks occur. ### Claim 8 A system, comprising: one or more processing units, comprising, a first type of in-order pipeline to receive at least one data prefetch instruction; at least one of a second type of in-order pipeline having issues slots to receive a plurality of instructions; and a data prefetch queue to receive the at least one data prefetch instruction and to issue the at least one data prefetch instruction to at least one of the second type of in-order pipeline upon at least one execution slot of the at least one of the second type of in-order pipeline being available or if desirable to preempt another instruction. ### Claim 9 (depends on 8) The system of claim 8, further comprising: an additional first type of in-order pipeline, wherein the first type of in-order pipelines are arithmetic logic unit (ALU) pipelines to receive ALU instructions and data prefetch instructions. ### Claim 10 (depends on 8) The system of claim 8, wherein the at least one of the second type of in-order pipeline comprises memory pipelines. ### Claim 11 (depends on 10) The system of claim 10, further comprising: one or more execution units to execute instructions associated with the execution slots of the memory pipelines. ### Claim 12 (depends on 11) The system of claim 11, further comprising: a software scheduler to determine whether to send the at least one data prefetch instruction to the first type of in-order pipelines or to the second type of in-order pipelines based on one or more factors including at least one of availability of one or more issue slots of the second type of in-order pipelines and priority of the at least one data prefetch instruction. ### Claim 13 (depends on 11) The system of claim 11, wherein the first type of in-order pipelines are integer pipelines to receive integer instructions and data prefetch instructions. ### Claim 14 (depends on 11) The system of claim 11, further comprising: memory coupled to the one or more processing units, wherein the one or more execution units of the memory pipelines to send data associated with the executed instructions to the memory. ### Claim 15 A computer-implemented method, comprising: determining whether to issue a data prefetch instruction to a first in-order pipeline or to a second in-order pipeline based on availability of one or more issue slots of the second in-order pipeline; receiving the data prefetch instruction with the first in-order pipeline based on one or more factors; issuing the data prefetch instruction to a data prefetch queue; and issuing the data prefetch instruction to the second in-order pipeline upon at least one execution slot of the second in-order pipeline being available. ### Claim 16 (depends on 15) The computer-implemented method of claim 15, wherein the first type of in-order pipeline is an arithmetic logic unit (ALU) pipeline to receive ALU instructions and data prefetch instructions, wherein the second in-order pipeline is a memory pipeline. ### Claim 17 (depends on 15) The computer-implemented method of claim 15, further comprising: receiving a plurality of other instructions with issues slots of the second in-order pipeline, wherein the one or more factors include at least one of no availability of one or more issue slots of the second in-order pipeline and priority of the data prefetch instruction. ### Claim 18 A machine-accessible medium including data that, when accessed by a machine, cause the machine to perform operations comprising: determining whether to issue a data prefetch instruction to a first in-order pipeline or to a second in-order pipeline based on availability of one or more issue slots of the second in-order pipeline; receiving the data prefetch instruction with the first in-order pipeline based on one or more factors; issuing the data prefetch instruction to a data prefetch queue; and issuing the data prefetch instruction to the second in-order pipeline upon at least one execution slot of the second in-order pipeline being available. ### Claim 19 (depends on 18) The machine-accessible medium of claim 18, wherein the first type of in-order pipeline is an arithmetic logic unit (ALU) pipeline to receive ALU instructions and data prefetch instructions, wherein the second in-order pipeline is a memory pipeline. ### Claim 20 (depends on 18) The machine-accessible medium of claim 18, further comprising: receiving a plurality of other instructions with issues slots of the second in-order pipeline, wherein the one or more factors include at least one of no availability of one or more issue slots of the second in-order pipeline and priority of the data prefetch instruction.