# US 2014/0195765 A1 · Implementing user mode foreign device attachment to memory channel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0195765 A1 - Document ID: US20140195765A1 - Status: Published application - Kind: A1 - Application number: 13/738,035 - Filed: 2013-01-10 - Published: 2014-07-10 - Earliest claimed: 2013-01-10 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Bulent Abali; Michele M. Franceschini; Luis A. Lastras-Montano - Web page: https://patentgrep.com/patent/US20140195765A1 ## CPC - G06F 12/10: Address translation - G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)} - G06F 11/1008: {in individual solid state devices (G06F11/1004 takes precedence)} - G06F 12/1081: for peripheral access to main memory, e.g. direct memory access [DMA] - G06F 12/145: {the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism} - G06F 2212/206: Memory mapped I/O - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method, system and computer program product are provided for implementing attachment of a user mode foreign device to a memory channel in a computer system. A user mode foreign device is attached to the memory channel using memory mapping of device registers and device buffers to the processor address space. The storage capacity on the device is doubly mapped in the address space creating separate control and data address spaces to allow user mode processes to control the device therefore eliminating the need for software system calls. A processor Memory Management Unit (MMU) coordinates multiple user processes accessing the device registers and buffers providing address space protection of each of interfaces, shifting device protection to the processor MMU from system software. ## Claims ### Claim 1 A method for implementing attachment of a user mode foreign device to a memory channel in a computer system comprising: attaching the user mode foreign device to the memory channel; using memory mapping of device registers and device buffers on the channel attached user mode foreign device to processor address space; doubly mapping storage capacity on the user mode foreign device in the processor address space creating separate control and data address spaces to allow user mode processes to control the channel attached user mode foreign device; and providing a processor Memory Management Unit (MMU) to coordinate multiple user processes accessing the device registers and buffers providing address space protection, and shifting device protection to the processor MMU from system software. ### Claim 2 (depends on 1) The method as recited in claim 1 wherein the user mode foreign device includes a flash storage device. ### Claim 3 (depends on 1) The method as recited in claim 1 wherein the user mode foreign device includes a Field Programmable Gate Array (FPGA). ### Claim 4 (depends on 1) The method as recited in claim 1 includes the channel attached device discovering ECC algorithm parameters. ### Claim 5 (depends on 4) The method as recited in claim 4 includes enabling the user mode foreign device to generate ECC bits and append the generated ECC bits to data. ### Claim 6 (depends on 1) The method as recited in claim 1 includes the channel attached device discovering bit-swizzling permutations. ### Claim 7 (depends on 6) The method as recited in claim 6 includes enabling the user mode foreign device to un-swizzle signals on wires of the memory channel. ### Claim 8 (depends on 1) The method as recited in claim 1 includes providing a device interface separated as control pages and data pages. ### Claim 9 (depends on 8) The method as recited in claim 8 includes multiple software processes controlling device operation through respective control pages and accessing device data through respective data pages. ### Claim 10 A system for implementing attachment of a user mode foreign device to a memory channel in a computer system comprising: the user mode foreign device attached to the memory channel; the user mode foreign device including a plurality of device registers and device buffers on the user mode foreign device memory for mapping to the processor address space, and doubly mapping storage capacity on the user mode foreign device in the address space creating separate control and data address spaces to allow user mode processes to control the device; and a processor Memory Management Unit (MMU) coordinating multiple user processes accessing the device registers and buffers and providing address space protection, shifting device protection to the processor MMU from system software. ### Claim 11 (depends on 10) The system as recited in claim 10 wherein the user mode foreign device includes a flash storage device. ### Claim 12 (depends on 10) The system as recited in claim 10 wherein the user mode foreign device includes a Field Programmable Gate Array (FPGA). ### Claim 13 (depends on 10) The system as recited in claim 10 includes a learn register and a bootstrap dictionary in the channel attached device discovering ECC algorithm parameters. ### Claim 14 (depends on 13) The system as recited in claim 13 wherein said bootstrap dictionary in the channel attached device enables the user mode foreign device to generate ECC bits and append the generated ECC bits to data. ### Claim 15 (depends on 13) The system as recited in claim 13 includes an ECC and bit swizzle encode/decode in the channel attached device discovering bit permutations on the memory channel. ### Claim 16 (depends on 15) The system as recited in claim 15 wherein said ECC and bit swizzle encode/decode in the channel attached device enables at least data permutation to be reversed upon reception of the data at the device. ### Claim 17 (depends on 15) The system as recited in claim 15 wherein said ECC and bit swizzle encode/decode in the channel attached device enables the user mode foreign device to un-swizzle signals on wires of the memory channel. ### Claim 18 (depends on 10) The system as recited in claim 10 wherein the user mode foreign device includes a device interface separated as control pages and data pages. ### Claim 19 (depends on 18) The system as recited in claim 18 includes multiple software processes controlling device operation through respective control pages and accessing device data through respective data pages. ### Claim 20 (depends on 18) The system as recited in claim 18 wherein said processor Memory Management Unit (MMU) providing address space protection of said device interface.