# US 2014/0195764 A1 · Memory device having an adaptable number of open rows

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- Number: US 2014/0195764 A1
- Document ID: US20140195764A1
- Status: Published application
- Kind: A1
- Application number: 13/736,662
- Filed: 2013-01-08
- Published: 2014-07-10
- Earliest claimed: 2013-01-08
- Assignees: QUALCOMM Incorporated
- Applicants: Qualcomm Incorporated
- Inventors: Jian Shen; Liyong Wang; Lew Chua-Eoan
- Web page: https://patentgrep.com/patent/US20140195764A1

## CPC

- G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0638: {Organizing or formatting or addressing of data}
- G06F 3/0653: {Monitoring storage devices or systems}
- G06F 3/0673: {Single storage device}
- G06F 12/0215: {with look ahead addressing means}
- G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F 12/10: Address translation
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G11C 7/1039: {using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers}
- G11C 8/06: Address interface arrangements, e.g. address buffers
- G11C 8/10: Decoders
- G11C 11/4082: {Address Buffers; level conversion circuits}
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G06F 12/0862: with prefetch
- G06F 2212/1016: Performance improvement
- G06F 2212/60: Details of cache memory
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A memory device comprises a memory array, at least one row address buffer, a set of row data buffers, a row decoder, an array of sense amplifiers, and a demultiplexer. The memory array comprises data elements organized into rows and columns. Each of the rows is addressable by a row address. Each of the data elements in each of the rows is addressable by a column address. The at least one row address buffer holds a selected row address of a set of successive selected row addresses. The set of row data buffers holds respective contents of selected rows that correspond to the set of successive selected row addresses. The row decoder decodes the selected row address to access a selected row. The array of sense amplifier reads the selected row and transmits content of the selected row to one of the row data buffers through the demultiplexer, and writes the content of the selected row back to the selected row.

## Claims

### Claim 1

A memory device comprising:
a memory array comprising data elements organized into rows and columns, each of the rows being addressable by a row address, each of the data elements in each of the rows being addressable by a column address;
at least one row address buffer for holding a selected row address of a set of successive selected row addresses;
a set of row data buffers for holding respective contents of selected rows corresponding to the set of successive selected row addresses;
a row decoder coupled to the at least one row address buffer and to the memory array for receiving the selected row address and for decoding the selected row address to access a selected row of the memory array;
an array of sense amplifiers coupled to the memory array and coupled to the set of row data buffers for reading the selected row and transmitting content of the selected row to one of the row data buffers, and for writing the content of the selected row back to the selected row; and
a demultiplexer coupled to the array of sense amplifiers and the set of row data buffers for providing the content of the selected row from the array of sense amplifiers to the one of the row data buffers.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the at least one row address buffer is a single register configured to hold the successive selected row addresses one at a time, the successive selected row addresses being dynamically computed from a first of the successive selected row addresses, and wherein the set of row data buffers is configured to hold contents of rows corresponding to the successive selected row addresses respectively.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the at least one row address buffer is a set of row address buffers configured to hold the set of successive selected row addresses respectively, the set of row address buffers corresponding to the set of row data buffers, the memory device further comprising:
a multiplexer coupled to the set of row address buffers and coupled to the row decoder for selecting a row address being held in a selected one of the row address buffers and for providing the selected row address to the row decoder.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein the array of sense amplifiers is configured to write the content of the selected row back to the selected row at completion of transmitting content of the selected row to the one of the row data buffers.

### Claim 5 (depends on 1)

The memory device of claim 1 further comprising:
a control circuit for receiving and decoding a first command, the first command including a specified row address and a row mode indicator, the row mode indicator specifying a number of rows to be open, the control circuit comprising a memory mode register for holding the row mode indicator.

### Claim 6 (depends on 5)

The memory device of claim 5, wherein the control circuit is configured to instruct the memory array to open the specified number of rows starting from the specified row address, contents of the opened specified number of rows being transferred to corresponding row data buffers for holding.

### Claim 7 (depends on 6)

The memory device of claim 6, wherein the control circuit is configured to receive a second command subsequent to the first command, the second command requesting a read from an identified row of the opened specified number of rows, and wherein the read of the identified row is performed by reading from a corresponding row data buffer.

### Claim 8 (depends on 6)

The memory device of claim 6, wherein the control circuit is configured to receive a third command subsequent to the first command, the third command requesting a write to an identified row of the opened specified number of rows, content of the identified row being held in a corresponding row data buffer, and wherein the write is performed by writing to the corresponding row data buffer.

### Claim 9 (depends on 6)

The memory device of claim 6, wherein the control circuit is configured to receive a fourth command subsequent to the first command, the fourth command requesting a precharge, the precharge being performed by writing back to the opened specified number of rows in the memory array one at a time using contents of the corresponding row data buffers and the array of sense amplifiers and closing the opened specified number of rows.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein the set of row data buffers comprises four row data buffers.

### Claim 11

A method of opening rows in a memory device, the memory device including a memory array comprising data elements organized into rows and columns, each of the rows being addressable by a row address, each of the data elements in each of the rows being addressable by a column address, the method comprising the operations of:
(a) receiving a first command to open a row, the command including a selected row address and a row mode indicator specifying a number of rows to open starting from the selected row address;
(b) loading the selected row address into at least one row address buffer;
(c) decoding the selected row address to access a selected row in the memory array using a row decoder;
(d) reading the selected row and transmitting content of the selected row to a corresponding row data buffer of a set of row data buffers using an array of sense amplifiers; and
if the specified number of rows to open is greater than one,
then:
(e) computing a successive selected row address based on the selected row address; and
(f) repeating operations (b), (c), and (d) with the selected row address being replaced by the successive selected row address.

### Claim 12 (depends on 11)

The method of claim 11, wherein the specified number of rows to open is equal to N where N is a number greater than two, the method further comprising:
repeating operations (e) and (f) until contents of the specified N rows read from the memory array are held in corresponding row data buffers of the set of row data buffers.

### Claim 13 (depends on 11)

The method of claim 11 further comprising:
receiving a second command subsequent to the first command, the second command requesting a read from an identified row of the opened specified number of rows, content of the identified row being held in a corresponding row data buffer; and
reading from the corresponding row data buffer in response to the second command.

### Claim 14 (depends on 11)

The method of claim 11 further comprising:
receiving a third command subsequent to the first command, the third command requesting a write to an identified row of the opened specified number of rows and comprising input data, content of the identified row being held in a corresponding row data buffer; and
writing the input data to the corresponding row data buffer holding content of the identified row.

### Claim 15 (depends on 11)

The method of claim 11 further comprising:
receiving a fourth command subsequent to the first command, the fourth command requesting a precharge;
writing back to the opened specified number of rows in the memory array one at a time using contents of the corresponding row data buffers and the array of sense amplifiers; and
closing the opened specified number of rows in the memory array.

### Claim 16

A memory controller for accessing a memory device, the memory device including a memory array comprising data elements organized into rows and columns, each of the rows being addressable by a row address, each of the data elements in each of the rows being addressable by a column address, the memory device being capable of having an adaptable number of open rows, the memory controller comprising:
an arbiter for receiving and scheduling a memory access request from a requestor, the memory access request including a logical address, the arbiter being configured to determine the adaptable number of open rows for the memory access request;
a memory mapper coupled to the arbiter for translating the logical address into a physical address including a row address and a column address; and
a command generator coupled to the memory mapper and the arbiter for generating a sequence of commands corresponding to the memory access request and for sending the sequence of commands to the memory device, one command of the sequence of commands including a row mode indicator specifying the adaptable number of open rows.

### Claim 17 (depends on 16)

The memory controller of claim 16 wherein the arbiter is configured to monitor a memory access pattern of the requestor to determine the adaptable number of open rows.

### Claim 18 (depends on 16)

The memory controller of claim 16 wherein the arbiter is configured to monitor the memory access pattern of the requestor by monitoring a ratio of row misses to row hits, and to determine the adaptable number of open rows to be more than one row when the ratio of row misses to row hits exceeds a threshold.

### Claim 19 (depends on 16)

The memory controller of claim 16 wherein the arbiter is configured to determine the adaptable number of open rows in accordance with an instruction received from a processor, the instruction specifying the adaptable number of open rows.

### Claim 20

A system comprising:
a memory device including a memory array comprising data elements organized into rows and columns, each of the rows being addressable by a row address, each of the data elements in each of the rows being addressable by a column address, the memory device being capable of having an adaptable number of open rows, the memory device comprising a set of row data buffers for holding contents of the adaptable number of open rows;
a memory controller configured to receive memory access requests from a requestor and coupled to the memory device for accessing the memory device; and
a processor coupled to the memory controller, the processor being capable of executing a row determination module included in the processor;
wherein the adaptable number of open rows is determined either by the memory controller from monitoring memory access pattern of the requestor or by the processor from executing the row determination module.