# US 2014/0195758 A1 · Block or page lock features in serial interface memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0195758 A1 - Document ID: US20140195758A1 - Status: Published application - Kind: A1 - Application number: 14/203,340 - Filed: 2014-03-10 - Published: 2014-07-10 - Earliest claimed: 2007-10-17 - Assignees: Micron Technology, Inc. - Inventors: Theodore T. Pekny - Web page: https://patentgrep.com/patent/US20140195758A1 ## CPC - G06F 12/1458: {by checking the subject access rights} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/14: Protection against unauthorised use of memory {or access to memory} - G06F 12/1425: {the protection being physical, e.g. cell, word, block} - G06F 13/1668: {Details of memory controller} - G06F 13/4068: {Electrical coupling} - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F 21/44: Program or device authentication - G06F 21/575: {Secure boot} - G06F 21/604: {Tools and structures for managing or administering access control systems} - G06F 21/81: by operating on the power supply, e.g. enabling or disabling power-on, sleep or resume operations - G06F 2212/1052: Security improvement - G06F 2221/2101: Auditing as a secondary aspect - G06F 2221/2117: User registration - G06F 2221/2147: Locking files - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Embodiments are provided for protecting boot block space in a memory device. Such a memory device may include a memory array having a protected portion and a serial interface controller. The memory device may have a register that enables or disables access to the portion when data indicating whether to enable or disable access to the portion is written into the register via a serial data in (SI) input. ## Claims ### Claim 1 A memory device comprising: a memory array; a serial interface controller having a serial data in (SI) input configured to receive a signal from a master device; and a register coupled to the serial interface controller, wherein the register is configured to enable or disable access to a portion of the memory array when data indicating whether to enable or disable access to the portion is written into the register via the SI input. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the data indicating whether to enable or disable access to the portion is configured to be written into the register via the SI input with a command accompanied by an address identifying the portion, wherein the command, the address, and the data are serially received on the SI input. ### Claim 3 (depends on 1) The memory device of claim 1, wherein the register being configured to enable or disable access to the portion comprises the register being configured to lock or unlock write access to the portion. ### Claim 4 (depends on 1) The memory device of claim 1, wherein the register being configured to enable or disable access to the portion comprises the register being configured to lock or unlock erase access to the portion. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the portion comprises an individual block of the memory array. ### Claim 6 (depends on 4) The memory device of claim 4, wherein the individual block of the memory array comprises a boot block. ### Claim 7 (depends on 1) The memory device of claim 1, wherein the portion comprises an individual page within a particular block of the memory array. ### Claim 8 (depends on 1) The memory device of claim 1, wherein the portion comprises a block region of the memory array. ### Claim 9 (depends on 8) The memory device of claim 8, wherein the block region is user-definable. ### Claim 10 (depends on 8) The memory device of claim 8, wherein the block region comprises an entire boot block space. ### Claim 11 (depends on 8) The memory device of claim 8, wherein the block region comprises a plurality of blocks. ### Claim 12 (depends on 1) The memory device of claim 1, wherein the register comprises a plurality of bits and wherein the portion is associated with a particular bit of the plurality of bits. ### Claim 13 (depends on 1) The memory device of claim 1, wherein the serial interface controller comprises a serial data out (SO) output, a serial clock (SCK) input, and a chip select (CS) input. ### Claim 14 (depends on 1) The memory device of claim 1, comprising a cache memory coupled to the controller by way of a first line, wherein the controller is coupled to the memory array by way of a second line and the cache memory is coupled to the memory array by way of a third line. ### Claim 15 (depends on 1) The memory device of claim 1, wherein the controller is configured to translate signals sent to the memory array into command latch enable (CLE), address latch enable (ALE) signal, write enable (WE), and read enable (RE) signals. ### Claim 16 (depends on 1) The memory device of claim 1, wherein the memory device is configured to authenticate the master device for accessing the portion of the memory array responsive to comparing a password entered by the master device to a stored password. ### Claim 17 (depends on 1) The memory device of claim 1, wherein the memory device is configured to authenticate the master device for accessing the memory array responsive to comparing a password entered by the master device to a stored password. ### Claim 18 (depends on 17) The memory device of claim 17, wherein the stored password is stored in the memory array. ### Claim 19 (depends on 1) The memory device of claim 1, wherein the register comprises a boot block access register. ### Claim 20 A system comprising: a master device; and a memory device, the memory device comprising: a memory array; a serial interface controller having a serial data in (SI) input configured to receive a signal from the master device; a register communicably coupled to the serial interface controller and configured to enable or disable access to a portion of the memory array responsive to a command addressing the portion and data indicating whether to enable or disable access to the portion, wherein the command addressing the portion and the data are serially received on the SI input from the master device. ### Claim 21 (depends on 20) The memory device of claim 20, wherein the master device comprises programmed control circuitry. ### Claim 22 (depends on 21) The memory device of claim 21, wherein the programmed control circuitry comprises a microcontroller. ### Claim 23 A system comprising: a master device; and a plurality of memory devices coupled to the master device, wherein each memory device of the plurality of memory devices comprises: a memory array; a serial interface controller having a serial data in (SI) input configured to receive a signal from the master device; a register communicably coupled to the serial interface controller and configured to enable or disable access to a portion of the memory array responsive to a command addressing the portion and data indicating whether to enable or disable access to the portion, wherein the command addressing the portion and the data are serially received on the SI input from the master device.