# US 2014/0195742 A1 · System on chip including memory management unit and memory address translation method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0195742 A1 - Document ID: US20140195742A1 - Status: Published application - Kind: A1 - Application number: 14/138,982 - Filed: 2013-12-23 - Published: 2014-07-10 - Earliest claimed: 2013-01-07 - Assignees: Samsung Electronics Co., Ltd. - Inventors: Seok Min KIM; Kwan Ho KIM; Seong Woon KIM; Tae Sun KIM; Kyoung Mook LIM - Web page: https://patentgrep.com/patent/US20140195742A1 ## CPC - G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] - G06F 12/023: {Free address space management} - G06F 12/0813: with a network or matrix configuration - G06F 12/1072: Decentralised address translation, e.g. in distributed shared memory systems - G06F 2212/306: In system interconnect, e.g. between two buses - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A system on chip (SoC) including a memory management unit (MMU) and a memory address translation method thereof are provided. The SoC includes a master intellectual property (IP) configured to output a request corresponding to each of a plurality of working sets; an MMU module comprising a plurality of MMUs, each of which is allocated for one of the working sets and translates virtual addresses corresponding to the request into physical addresses; a first bus interconnect configured to connect the MMU module with a memory device and to transmit the request, on which address translation has been performed in at least one of the MMUs, to the memory device; and a second bus interconnect configured to connect the master IP with the MMU module and to allocate one of the MMUs for each of the working sets. ## Claims ### Claim 1 A system on chip (SoC) comprising: a master intellectual property (IP) configured to output a request corresponding to each of a plurality of working sets; a memory management unit (MMU) module including a plurality of MMUs, each of which is allocated for one of the working sets and is configured to translate virtual addresses corresponding to the request into physical addresses; and a first bus interconnect configured to connect the MMU module with a memory device and to transmit the request, on which address translation has been performed in at least one of the plurality of MMUs, to the memory device. ### Claim 2 (depends on 1) The SoC of claim 1, wherein each of the plurality of working sets is a set of pages frequently referred to in the memory device by the master IP, and is managed independently from other working sets in the master IP. ### Claim 3 (depends on 1) The SoC of claim 1, wherein the plurality of MMUs in the MMU module are configured to operate independently from each other for respective working sets from among the plurality of working sets. ### Claim 4 (depends on 1) The SoC of claim 1, wherein the plurality of working sets include a read working set and a write working set, and the MMU module includes, a first MMU configured to access the read working set in the memory device according to a read request of the master IP; and a second MMU configured to access the write working set in the memory device according to a write request of the master IP. ### Claim 5 (depends on 4) The SoC of claim 4, wherein the first MMU is connected with the master IP through a read channel and the second MMU is connected with the master IP through a write channel. ### Claim 6 (depends on 4) The SoC of claim 4, wherein the first bus interconnect is configured to connect to the read working set in the memory device when receiving the read request from the first MMU and configured to connect to the write working set in the memory device when receiving the write request from the second MMU. ### Claim 7 (depends on 1) The SoC of claim 1, wherein the plurality of working sets include a source set and a destination set, and the MMU module includes, a first MMU configured to access the source set in the memory device according to a source access request of the master IP; and a second MMU configured to access the destination set in the memory device according to a destination access request of the master IP. ### Claim 8 (depends on 7) The SoC of claim 7, further comprising a second bus interconnect configured to connect the master IP with the MMU module and to dynamically allocate either of the first and second MMUs according to the request of the master IP. ### Claim 9 (depends on 8) The SoC of claim 8, wherein the second bus interconnect is configured to connect to the first MMU when receiving the source access request from the master IP and configured to connect to the second MMU when receiving the destination access request from the master IP. ### Claim 10 A system on chip (SoC) comprising: a master intellectual property (IP) configured to output a request corresponding to each of a plurality of working sets; a memory management unit (MMU) module comprising a plurality of MMUs, each of which is allocated for one of the working sets and is configured to translate virtual addresses corresponding to the request into physical addresses; a first bus interconnect configured to connect the MMU module with a memory device and to transmit the request, on which address translation has been performed in at least one of the plurality of MMUs, to the memory device; and a second bus interconnect configured to connect the master IP with the MMU module and to allocate one of the MMUs for each of the plurality of working sets. ### Claim 11 (depends on 10) The SoC of claim 10, wherein the plurality of working sets are stored in the memory device and each of the plurality of working sets is a set of pages frequently referred to in the memory device by the master IP and a data set managed independently from other working sets from among the plurality of working sets. ### Claim 12 (depends on 10) The SoC of claim 10, wherein the MMUs in the MMU module operate independently from each other for respective working sets from among the plurality of working sets. ### Claim 13 (depends on 10) The SoC of claim 10, further comprising: an address distributor configured to store MMU allocation information corresponding to each of the working sets, wherein the address distributor outputs an identification (ID) of an MMU corresponding to the request based on the MMU allocation information when receiving the request from the master IP. ### Claim 14 (depends on 13) The SoC of claim 13, wherein the address distributor comprises: a register set configured to store the MMU allocation information corresponding to each working set; and an address comparator configured to compare the MMU allocation information with a virtual address corresponding to the request received from the master IP and to output the MMU ID corresponding to the request. ### Claim 15 (depends on 14) The SoC of claim 14, wherein the register set is configured to map an indicator among consecutive virtual addresses corresponding to each of the working sets to the MMU ID and stores the mapping information as the MMU allocation information. ### Claim 16 (depends on 15) The SoC of claim 15, wherein the address comparator is configured to compare the virtual address corresponding to the request with the indicator and configured to output the MMU ID allocated for the working set. ### Claim 17 (depends on 10) The SoC of claim 10, wherein the first bus interconnect and the second bus interconnect are configured to connect to a port of an MMU dynamically allocated among the plurality of MMUs according to the request of the master IP and a response of the memory device. ### Claim 18 A memory address translation method comprising: outputting a request for each of a plurality of working sets, which are processed by a master intellectual property (IP), using the master IP; allocating one of a plurality of memory management units (MMUs) for each working set; translating virtual addresses corresponding to the request into physical addresses using the allocated MMU; and transmitting the address-translated request to the physical addresses of a memory device. ### Claim 19 (depends on 18) The memory address translation method of claim 18, wherein the plurality of working sets are stored in the memory device and each of the plurality of working sets is a set of pages frequently referred to in the memory device by the master IP and a data set managed independently from other working sets. ### Claim 20 (depends on 18) The memory address translation method of claim 18, wherein the plurality of MMUs operate independently from each other for the respective working sets. ### Claim 21 (depends on 18) The memory address translation method of claim 18, wherein the allocating one of the MMUs comprises: storing MMU allocation information corresponding to each of the plurality of working sets; comparing the virtual addresses corresponding to the request with the MMU allocation information in response to the request of the master IP; and outputting an identification (ID) of the MMU corresponding to the request based on the MMU allocation information as a result of the comparison. ### Claim 22 (depends on 18) The memory address translation method of claim 18, further comprising: for each of the plurality of working sets, processing the working set at the physical addresses according to the request and outputting a response or data corresponding to a processing result using the memory device; transmitting the response or the data to the MMU allocated for the working set among the plurality of MMUs; and transmitting the response or the data to the master IP. ### Claim 23 (depends on 22) The memory address translation method of claim 22, wherein the response includes the ID of the MMU allocated for the processed working set. ### Claim 24 An electronic system comprising: a master intellectual property (IP) configured to output a request corresponding to each of a plurality of working sets; a memory management unit (MMU) module including a plurality of MMUs, each of which is allocated for one of the plurality of working sets and is configured to translate virtual addresses corresponding to the request into physical addresses; a memory device configured to process each request of the master IP and to transmit a response or data corresponding to the request; a first bus interconnect configured to connect the MMU module with the memory device, configured to transmit each request of the plurality of MMUs to the memory device, and configured to transmit the response or the data corresponding to the request processed by the memory device to the MMU module; and a second bus interconnect configured to, connect the master IP with the MMU module, allocate one of the plurality of MMUs for each of the working sets, transfer each request of the master IP to the allocated MMU, and transmit the response or the data from the allocated MMU to the master IP. ### Claim 25 (depends on 24) The electronic system of claim 24, wherein the second bus interconnect stores MMU allocation information corresponding to each of the plurality of working sets and is configured to connect the MMU corresponding to the request based on the MMU allocation information when receiving the request from the master IP. ### Claim 26 A system on chip (SoC) comprising: a master intellectual property (IP) configured to output one or more requests corresponding to a first working set of data and a second working set of data; and a memory management unit (MMU) module including, a first MMU configured to perform a first translation operation including translating a virtual address of the first working set of data into a physical address, and a second MMU configured to perform a second translation operation including translating a virtual address of the second working set of data into a physical address, wherein the MMU module is configured such that the first and second MMUs are different units and the first and second translation operations are performed by the first and second MMUs simultaneously. ### Claim 27 (depends on 26) The system on chip (SoC) of claim 26, wherein, the first MMU includes a first memory buffer and is configured to perform the first translation operation by using the first memory buffer, and the second MMU includes a second memory buffer and is configured to perform the second translation operation by using the second memory buffer. ### Claim 28 (depends on 27) The system on chip (SoC) of claim 27, wherein the first and second memory buffers are translation lookaside buffers (TLBs). ### Claim 29 (depends on 26) The system on chip (SoC) of claim 26, further comprising: a first bus interconnect configured to connect the MMU module with a memory device and to transmit the request to the memory device, the first and second working sets of data being stored in the memory device.