# US 2014/0195729 A1 · Memory Having Improved Reliability for Certain Data Types

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- Number: US 2014/0195729 A1
- Document ID: US20140195729A1
- Status: Published application
- Kind: A1
- Application number: 13/736,310
- Filed: 2013-01-08
- Published: 2014-07-10
- Earliest claimed: 2013-01-08
- Assignees: Freescale Semiconductor, Inc.
- Inventors: Andrew C. Russell; Ravindraraj Ramaraju
- Web page: https://patentgrep.com/patent/US20140195729A1

## CPC

- G06F 11/004: {Error avoidance (G06F11/07 and subgroups take precedence)}
- G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)}
- G06F 11/1064: {in cache or content addressable memories}
- G06F 12/0846: Cache with multiple tag or data arrays being simultaneously accessible
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method for minimizing soft error rates within caches by configuring a cache with certain sections to correspond to bitcell topologies that are more resistant to soft errors and then using these sections to store modified data.

## Claims

### Claim 1

A cache system comprising:
a cache array, the cache array comprising a plurality of sections, at least one of the sections comprising bitcells configured with an error resistant bitcell topology and at least another of the sections comprising bitcells configured with a less error resistant bitcell topology; and,
cache control logic, the cache control logic determining whether information to be written to the cache array comprises modified information, the cache control logic storing the modified information to the at least one of the sections comprising the cells configured with the error resistant bitcell topology.

### Claim 2 (depends on 1)

The cache system of claim 1 wherein:
the cache control logic determines whether the section configured with the error resistant bitcell topology contains valid modified information and if so, the cache control logic evicts the valid modified information from the section configured with the error resistant bitcell topology and writes the modified information to the section configured with the error resistant bitcell topology.

### Claim 3 (depends on 2)

The cache system of claim 2 wherein:
the cache control logic stores unmodified information to the at least one other of the sections.

### Claim 4 (depends on 1)

The cache system of claim 1 wherein:
the error resistant bitcell topology comprises bitcells with a dynamic random access memory (DRAM) type bitcell topology; and,
the less error resistant bitcell topology comprises bitcells with a static random access memory (SRAM) type bitcell topology.

### Claim 5 (depends on 1)

The cache system of claim 1 wherein:
the error resistant bitcell topology comprises bitcells with a first plurality of transistors; and,
the less error resistant bitcell topology comprises bitcells with a second plurality of transistors, the second plurality of transistors being less than the first plurality of transistors.

### Claim 6 (depends on 5)

The cache system of claim 5 wherein:
the first plurality of transistors corresponds to a twelve transistor configuration and the second plurality of transistors corresponds to a six transistor configuration.

### Claim 7 (depends on 5)

The cache system of claim 5 wherein:
the first plurality of transistors corresponds to a dual interlocked cell (DICE) configuration and the second plurality of transistors corresponds a cross coupled inverter cell configuration.

### Claim 8 (depends on 1)

The cache system of claim 1 wherein:
each of the sections are characterized as ways.

### Claim 9

A method for improving error resilience comprising:
providing a cache array, the cache array comprising a plurality of sections, at least one of the sections comprising bitcells configured with an error resistant bitcell topology at least another of the sections comprising bitcells configured with a less error resistant bitcell topology;
determining whether data to be written to the cache array comprises modified information; and,
storing the modified information to the at least one of the sections configured via the error resistant bitcell topology.

### Claim 10 (depends on 9)

The method of claim 9 further comprising:
determining whether the section configured with the error resistant bitcell topology contains valid modified information and if so, evicting the valid modified information from the section configured with the error resistant bitcell topology and writing the modified information to the section configured with the error resistant bitcell topology.

### Claim 11 (depends on 9)

The method of claim 9 further comprising:
storing unmodified information to the at least one other of the sections.

### Claim 12 (depends on 9)

The method of claim 9 further comprising:
the error resistant bitcell topology comprises bitcells with a dynamic random access memory (DRAM) type bitcell topology; and,
the less error resistant bitcell topology comprises bitcells with a static random access memory (SRAM) type bitcell topology.

### Claim 13 (depends on 9)

The method of claim 9 wherein:
the error resistant bitcell topology comprises bitcells with a first plurality of transistors; and,
the less error resistant bitcell topology comprises bitcells with a second plurality of transistors, the second plurality of transistors being less than the first plurality of transistors.

### Claim 14 (depends on 13)

The method of claim 13 wherein:
the first plurality of transistors corresponds to a twelve transistor configuration and the second plurality of transistors corresponds to a six transistor configuration.

### Claim 15 (depends on 13)

The method of claim 13 wherein:
the first plurality of transistors corresponds to a dual interlocked cell (DICE) configuration and the second plurality of transistors corresponds to a cross coupled inverter cell configuration.

### Claim 16 (depends on 9)

The method of claim 9 wherein:
each of the sections are characterized as ways.

### Claim 17

A memory comprising:
a first plurality of bitcells and a second plurality of bitcells, the first plurality of bitcells comprising bitcells having an error resistant topology and the second plurality of bitcells comprising bitcells having to another topology;
a controller, the controller storing modified data only in the first plurality of bitcells.

### Claim 18 (depends on 17)

The memory of claim 17 wherein:
the error resistant topology is characterized as a dynamic random access memory (DRAM) type topology; and,
the another topology is characterized as a static random access memory (SRAM) type topology.

### Claim 19 (depends on 17)

The memory of claim 17 wherein:
each bitcell of the first plurality of bitcells has a first plurality of transistors; and,
each bitcell of the second plurality of bitcells has a second plurality of transistors, the second plurality of transistors being less than the first plurality of transistors.

### Claim 20 (depends on 17)

The memory of claim 17 wherein:
each bitcell of the first plurality of bitcells is characterized as a dual interlocked cell (DICE) configuration; and,
each bitcell of the second plurality of bitcells is characterized as an interlocked cell configuration.

### Claim 21 (depends on 17)

The memory of claim 17 wherein:
each bitcell of the first plurality of bitcells is characterized as a dynamic random access memory (DRAM) type bitcell topology; and,
each bitcell of the second plurality of bitcells is characterized as a static random access memory (SRAM) type bitcell topology.

### Claim 22 (depends on 17)

The memory of claim 17 wherein:
the memory is characterized as a cache memory.