# US 2014/0195724 A1 · Apparatus and method of converting address and data of memory in a terminal

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- Number: US 2014/0195724 A1
- Document ID: US20140195724A1
- Status: Published application
- Kind: A1
- Application number: 14/149,665
- Filed: 2014-01-07
- Published: 2014-07-10
- Earliest claimed: 2013-01-07
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd
- Inventors: Hee-Sub Shin
- Web page: https://patentgrep.com/patent/US20140195724A1

## CPC

- G06F 12/0638: {Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module (address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70)}
- G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/1408: {by using cryptography (for digital transmission H04L9/00)}
- G06F 21/85: interconnection devices, e.g. bus-connected or in-line devices
- G11C 14/0081: {and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An apparatus and method of converting an address and data of a memory in a terminal. The apparatus includes a random key generator configured to generate a new random key, each time the terminal is powered on, an address mapper configured to convert an address of a memory area for data writing or reading using the random key and transmit the converted address to a data converter, and the data converter configured to convert data to be written to the memory using the converted address and convert data to read from the memory using the converted address to original data.

## Claims

### Claim 1

An apparatus for converting a memory address in a terminal, the apparatus comprising:
a random key generator configured to generate a new random key each time the terminal is powered on; and
an address mapper configured to convert an address of a memory area for data writing or reading using the generated random key and transmit the converted address to a memory, to write data to or read data from a memory area corresponding to the converted address.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein when the terminal is powered on in a power saving mode, the random key generator is configured to not generate a random key.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein when the terminal is powered on in a power saving mode, the random key generator is configured to generate a same random key as a previous random key.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the address mapper is configured to convert a first address value of a memory area for data writing or reading to a second address value using the generated random key and transmit the second address value to the memory.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the address mapper is configured to convert the first address value to the second address value using the generated random key in a one-to-one correspondence.

### Claim 6 (depends on 4)

The apparatus of claim 4, wherein each time the new random key is generated, the address mapper is configured to convert the first address value to a different second address value using the new random key.

### Claim 7 (depends on 1)

The apparatus of claim 1, further comprising:
a processor configured to extract an address of a memory area for data writing or reading and transmit the extracted address to the address mapper; and
the memory configured to, in response to receipt of the converted address from the address mapper, write data to or read data from the memory area corresponding to the converted address.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein if the first address value of the memory area is a predetermined address excluded from address conversion, the processor is configured to transmit the first address value to the memory without transmitting the first address value to the address mapper.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein upon receipt of the first address value from the processor, the memory is configured to write data to or read data from the memory area corresponding to the first address value.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein at least some components of the random key generator and the address mapper are implemented by the processor.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein at least some components of the random key generator and the address mapper are included in the memory.

### Claim 12 (depends on 1)

The apparatus of claim 1, wherein the memory is a Non-Volatile Random Access Memory (NVRAM).

### Claim 13

An apparatus for converting an address and data of a memory in a terminal, the apparatus comprising:
a random key generator configured to generate a new random key each time the terminal is powered on;
an address mapper configured to convert an address of a memory area for data writing or reading using the generated random key and transmit the converted address to a data converter; and
the data converter configured to convert data to be written to the memory using the converted address and convert data to read from the memory using the converted address to original data.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein when the terminal is powered on in a power saving mode, the random key generator is configured to not generate a random key or generate a same random key as a previous random key.

### Claim 15 (depends on 13)

The apparatus of claim 13, wherein the address mapper is configured to map a first address value of a memory area to a second address value using the generated random key and transmit the second address value to the memory and the data converter.

### Claim 16 (depends on 13)

The apparatus of claim 13, wherein if a first address value of a memory area is a predetermined address excluded from address conversion, the address mapper is configured to transmit the first address value to the memory, map the first address value to a second address value using the generated random key, and transmit the second address value to the data converter.

### Claim 17 (depends on 15)

The apparatus of claim 15, wherein the address mapper is configured to map the first address value to the second address value using the random key in a one-to-one correspondence.

### Claim 18 (depends on 15)

The apparatus of claim 15, wherein each time a new random key is generated, the address mapper is configured to map the first address value to a different second address value using the new random key.

### Claim 19 (depends on 13)

The apparatus of claim 13, further comprising:
a processor configured to transmit data to be written to the memory to the data converter and transmit an address of a memory area for data writing or reading to the address mapper; and
the memory configured to write converted data received from the data converter to a memory area corresponding to a converted address received from the address mapper, extract converted data from a memory area corresponding to a converted address received from the address mapper, and transmit the extracted data to the data converter.

### Claim 20 (depends on 19)

The apparatus of claim 19, wherein if data writing is requested, the memory is configured to write the converted data received from the data converter in the memory area corresponding to the address received from the address mapper, and if data reading is requested, the memory is configured to extract the converted data from the memory area corresponding to the address received from the address mapper.

### Claim 21 (depends on 13)

The apparatus of claim 13, wherein at least some components of the random key generator, the address mapper, and the data converter are implemented by in the processor.

### Claim 22 (depends on 13)

The apparatus of claim 13, wherein at least some components of the random key generator, the address mapper, and the data converter are included in the memory.

### Claim 23 (depends on 13)

The apparatus of claim 13, wherein the memory is a Non-Volatile Random Access Memory (NVRAM).

### Claim 24

An apparatus for converting an address and data of a memory in a terminal, the apparatus comprising:
a processor configured to transmit data to be written to the memory and an address of a memory area for data writing or reading to a conversion unit;
the conversion unit configured to convert the address of the memory area for data writing or reading using a random key that is generated each time the terminal is powered on, transmit the converted address to the memory, convert the data to be written to the memory, transmit the converted data to the memory, and return converted data read from the memory to original data; and
the memory configured to write the converted data received from the conversion unit in a memory area corresponding to the converted address received from the conversion unit, extract the converted data from the memory area corresponding to the converted address received from the conversion unit, and transmit the extracted data to the conversion unit.

### Claim 25 (depends on 24)

The apparatus of claim 24, wherein the conversion unit includes:
a random key generator configured to generate a new random key each time the terminal is powered on;
an address mapper configured to convert the address of the memory area for data writing or reading using the generated random key and transmit the converted address to a data converter; and
the data converter configured to convert the data to be written to the memory using the converted address and return the converted data read from the memory to the original data using the converted address.

### Claim 26 (depends on 25)

The apparatus of claim 25, wherein when the terminal is powered on in a power saving mode, the random key generator is configured to not generate a random key or generate a same random key as a previous random key.

### Claim 27 (depends on 25)

The apparatus of claim 25, wherein the address mapper is configured to map a first address value of a memory area to a second address value using the random key and transmit the second address value to the memory and the data converter.

### Claim 28 (depends on 25)

The apparatus of claim 25, wherein if a first address value of a memory area is a predetermined address excluded from address conversion, the address mapper is configured to transmit the first address value to the memory, map the first address value to a second address value using the generated random key, and transmit the second address value to the data converter.

### Claim 29 (depends on 27)

The apparatus of claim 27, wherein the address mapper is configured to map the first address value to the second address value using the generated random key in a one-to-one correspondence.

### Claim 30 (depends on 29)

The apparatus of claim 29, wherein each time a new random key is generated, the address mapper is configured to map the first address value to a different second address value using the new random key.

### Claim 31 (depends on 24)

The apparatus of claim 24, wherein the memory is configured to write converted data received from the conversion unit in a memory area corresponding to an address received from the conversion unit, extract converted data from a memory area corresponding to an address received from the conversion unit, and transmit the extracted data to the conversion unit.

### Claim 32 (depends on 24)

The apparatus of claim 24, wherein at least some components of the conversion unit is implemented by in the processor.

### Claim 33 (depends on 24)

The apparatus of claim 24, wherein at least some components of the conversion unit is included in the memory.

### Claim 34 (depends on 24)

The apparatus of claim 24, wherein the memory is a Non-Volatile Random Access Memory (NVRAM).

### Claim 35

A method of converting an address of a memory in a terminal, the method comprising:
generating a new random key when the terminal is powered on;
converting an address of a memory area for data writing or reading using the generated random key; and
writing data to or reading data from a memory area corresponding to the converted address.

### Claim 36 (depends on 35)

The method of claim 35, wherein generating the new random key comprises generating a new random key each time the terminal is powered on.

### Claim 37 (depends on 35)

The method of claim 35, further comprising:
generating no random key if the terminal is powered on in a power saving mode; and
converting an address of a memory area for data writing or reading using a random key generated before the power saving mode.

### Claim 38 (depends on 35)

The method of claim 35, further comprising generating a same random key as a previous random key if the terminal is powered on in a power saving mode.

### Claim 39 (depends on 35)

The method of claim 35, wherein the conversion comprises:
receiving a first address value of the memory area for data writing or reading to a second address value;
converting the first address value to a second address value using the generated random key.

### Claim 40 (depends on 39)

The method of claim 39, further comprising, if the first address value of the memory area for data writing or reading is a predetermined address excluded from address conversion, writing or reading data to or from the memory area corresponding to the first address value.

### Claim 41 (depends on 39)

The method of claim 39, wherein converting the first address value to the second address value comprises converting the first address value to the second address value using the random key in a one-to-one correspondence.

### Claim 42 (depends on 39)

The method of claim 39, wherein each time a new random key is generated, converting the first address value to the second address value comprises converting the first address value to a different second address value using the new random key.

### Claim 43 (depends on 35)

The method of claim 35, wherein the memory is a Non-Volatile Random Access Memory (NVRAM).

### Claim 44

A method of converting an address and data of a memory in a terminal, the method comprising:
generating a new random key when the terminal is powered on;
converting an address of a memory area for data writing or reading using the random key;
converting data to be written to the memory using the converted address and writing the converted data in a memory area corresponding to the converted address in response to request of data writing; and
extracting the converted data from the memory area corresponding to the converted address and converting the extracted data to original data in response to request of data reading.

### Claim 45 (depends on 44)

The method of claim 44, wherein generating the new random key comprises generating a new random key each time the terminal is powered on.

### Claim 46 (depends on 44)

The method of claim 44, further comprising:
generating no random key if the terminal is powered on in a power saving mode; and
converting an address of a memory area for data writing or reading using a random key generated before the power saving mode.

### Claim 47 (depends on 44)

The method of claim 44, further comprising generating a same random key as a previous random key if the terminal is powered on in a power saving mode.

### Claim 48 (depends on 44)

The method of claim 44, wherein converting the address of the memory area for data writing or reading comprises:
receiving a first address value of the memory area for data writing or reading to a second address value;
converting the first address value to the second address value using the random key.

### Claim 49 (depends on 44)

The method of claim 44, wherein converting data to be written to the memory using the converted address and writing the converted data in the memory area corresponding to the converted address comprises:
converting first data to be written to second data using a converted second address value, in response to request of data writing; and
storing the second data in a memory area corresponding to the second address value.

### Claim 50 (depends on 44)

The method of claim 44, wherein converting data to be written to the memory using the converted address and writing the converted data in the memory area corresponding to the converted address comprises:
converting first data to be written to second data using a converted second address value in response to request of data writing; and
storing the second data in a memory area corresponding to the first address value if the first address value is excluded from address conversion.

### Claim 51 (depends on 44)

The method of claim 44, wherein extracting the converted data from the memory area corresponding to the converted address and converting the extracted data to original data comprises:
extracting converted second data from a memory area corresponding to a converted second address value in response to request of data reading; and
converting the second data to first data being original data.

### Claim 52 (depends on 44)

The method of claim 44, wherein extracting the converted data from the memory area corresponding to the converted address and converting the extracted data to original data comprises:
extracting converted second data from a memory area corresponding to a first address value in response to request of data reading if the first address value is excluded from address conversion; and
converting the second data to first data being original data.

### Claim 53 (depends on 48)

The method of claim 48, wherein converting the address of the memory area for data writing or reading comprises converting the first address value to the second address value using the generated random key in a one-to-one correspondence.

### Claim 54 (depends on 48)

The method of claim 48, wherein each time a new random key is generated, converting the first address value to the second address value comprises converting the first address value to a different second address value using the new random key.

### Claim 55 (depends on 44)

The method of claim 44, wherein the memory is a Non-Volatile Random Access Memory (NVRAM).