# US 2014/0195723 A1 · Non-volatile configuration for serial non-volatile memory

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- Number: US 2014/0195723 A1
- Document ID: US20140195723A1
- Status: Published application
- Kind: A1
- Application number: 14/148,079
- Filed: 2014-01-06
- Published: 2014-07-10
- Earliest claimed: 2011-09-26
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Paolo Rolandi; Sandra Lospalluti; Raffaele Bufano; Stefano Andreoli; Tommaso Zerilli
- Web page: https://patentgrep.com/patent/US20140195723A1

## CPC

- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 9/44573: {Execute-in-place [XIP]}
- G11C 16/10: Programming or data input circuits
- G11C 16/20: Initialising; Data preset; Chip identification
- G06F 2212/72: Details relating to flash memory management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Example embodiments for configuring a serial non-volatile memory device may comprise a non-volatile configuration register to store a configuration value received from the processor, the configuration value to specify one or more attributes of a memory access operation. The configuration value may be read at least in part in response to power being applied to the memory device.

## Claims

### Claim 1

(canceled)

### Claim 2

An apparatus comprising a serial non-volatile memory device, the apparatus comprising:
a non-volatile configuration register configured to store a configuration value; and
a control unit configured to read the configuration value from the non-volatile configuration register at least when the serial non-volatile memory device is powered up, wherein the control unit is configured to adjust an output driver strength of the serial non-volatile memory device for a read operation based on the configuration value, wherein at least a portion of the configuration value specifies the output driver strength.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the configuration value specifies an output driver strength in the range of 15 ohms to 90 ohms.

### Claim 4 (depends on 2)

The apparatus of claim 2, wherein the non-volatile configuration register comprises a plurality of flash memory cells.

### Claim 5 (depends on 2)

The apparatus of claim 2, wherein the non-volatile configuration register is configured to be updated at least in part in response to the serial non-volatile memory device receiving a subsequent configuration value from a processor.

### Claim 6 (depends on 2)

The apparatus of claim 2, wherein the serial non-volatile memory device comprises a serial flash memory device.

### Claim 7 (depends on 2)

The apparatus of claim 2, wherein the configuration value further specifies a minimum time before first access after power-up for the serial non-volatile memory device, and wherein the control unit is further configured to inhibit memory access operations until the minimum time elapses.

### Claim 8 (depends on 2)

The apparatus of claim 2, wherein the configuration value further specifies an execute-in-place mode for the read operation.

### Claim 9

An electronically-implemented method of configuring a serial non-volatile memory device, the method comprising:
reading a configuration value in a non-volatile configuration register of a serial non-volatile memory device at least in part in response to power being applied to the serial non-volatile memory device; and
adjusting an output driver strength of the serial non-volatile memory device for a read operation based on the configuration value, wherein at least a portion of the configuration value specifies the output driver strength.

### Claim 10 (depends on 9)

The method of claim 9, wherein the configuration value specifies an output driver strength in the range of 15 ohms to 90 ohms.

### Claim 11 (depends on 9)

The method of claim 9, wherein the non-volatile configuration register comprises a plurality of flash memory cells.

### Claim 12 (depends on 9)

The method of claim 9, further comprising updating the non-volatile configuration register at least in part in response to the serial non-volatile memory device receiving a subsequent configuration value from a processor.

### Claim 13 (depends on 9)

The method of claim 9, wherein the serial non-volatile memory device comprises a serial flash memory device.

### Claim 14 (depends on 9)

The method of claim 9, wherein the configuration value further specifies a minimum time before first access after power-up for the serial non-volatile memory device, and further comprising inhibiting memory access operations until the minimum time elapses.

### Claim 15 (depends on 9)

The method of claim 9, wherein the configuration value further specifies an execute-in-place mode for the read operation.

### Claim 16

A system, comprising:
a processor; and
a serial non-volatile memory device coupled to the processor, the memory device comprising:
a non-volatile configuration register configured to store a configuration value; and
a control unit configured to read the configuration value from the non-volatile configuration register at least when the serial non-volatile memory device is powered up, wherein the control unit is configured to adjust an output driver strength of the serial non-volatile memory device for a read operation based on the configuration value, wherein at least a portion of the configuration value specifies the output driver strength.

### Claim 17 (depends on 16)

The system of claim 16, wherein the configuration value specifies an output driver strength in the range of 15 ohms to 90 ohms.

### Claim 18 (depends on 16)

The system of claim 16, wherein the non-volatile configuration register comprises a plurality of flash memory cells.

### Claim 19 (depends on 16)

The system of claim 16, wherein the serial non-volatile memory device comprises a serial flash memory device.

### Claim 20 (depends on 16)

The system of claim 16, wherein the configuration value further specifies a minimum time before first access after power-up for the serial non-volatile memory device, and wherein the control unit is further configured to inhibit memory access operations until the minimum time elapses.

### Claim 21 (depends on 16)

The system of claim 16, wherein the configuration value further specifies an execute-in-place mode for the read operation.
