# US 2014/0195718 A1 · Control logic design to support usb cache offload

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- Number: US 2014/0195718 A1
- Document ID: US20140195718A1
- Status: Published application
- Kind: A1
- Application number: 13/735,720
- Filed: 2013-01-07
- Published: 2014-07-10
- Earliest claimed: 2013-01-07
- Assignees: LSI Corporation
- Applicants: Lsi Corporation
- Inventors: Moby J. Abraham; Lakshmana M. Anupindi; R. Brian B. Skinner; James A. Rizzo; Mark J. Jander
- Web page: https://patentgrep.com/patent/US20140195718A1

## CPC

- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 9/00: Arrangements for program control, e.g. control units (program control for peripheral devices G06F13/10)
- G06F 11/00: Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00)
- G06F 11/1441: {Resetting or repowering}
- G06F 12/0804: with main memory updating (G06F12/0806 takes precedence)
- G06F 1/30: Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24)
- G06F 11/2015: {Redundant power supplies (power supply failure G06F1/30)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A redundant array of independent drives controller and board controlled cache off-loading during a power failure is described. Methods associated with the use of the redundant array of independent drives controller and board for controlled cache off-loading during a power failure are also described.

## Claims

### Claim 1

A method for controlling cache offload during a power failure comprising:
monitoring a power supply from a host peripheral component interconnect express connector unit to a redundant array of independent drives controller;
identifying when a power failure from said power supply to said redundant array of independent drives controller has taken place;
identifying whether a cache offload is required from said redundant array of independent drives controller cache to a non-volatile storage device at the time of power loss;
preparing said redundant array of independent drives controller for a cache off-load during said power failure;
off-loading said cache from said redundant array of independent drives controller during said power failure; and
proceeding to boot or power down said redundant array of independent drives controller after said cache offload from said redundant array of independent drives controller has been completed.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
initiating a power loss latch mode once said power failure has been identified; and
enabling an alternate power source to the redundant array of independent drives controller once said power failure is identified

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
monitoring if said power loss latch mode has been asserted and enabling an alternate clock source for said redundant array of independent drives controller;

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
continuing to monitor is said power loss latch mode for said redundant array of independent drives controller has asserted;
if said power loss latch mode has been asserted, setting an internal offload boot flag in said redundant array of independent drives controller if said cache offload has been identified to be off-loaded from said redundant array of independent drives controller to a non-volatile storage device at the time of said power loss;
initializing modules needed for said cache offload;
said redundant array of independent drives controller checking if said boot flag cache is said offload boot flag;
initializing all of the modules needed for a universal serial bus offload; and
starting cache offload and continuing until completion.

### Claim 5 (depends on 4)

The method of claim 4, further comprising
identifying if said cache offload boot flag is set;
initiating said redundant array of independent drives controller to copy the contents of said cache into a non-volatile memory;
copying said contents of said cache into said non-volatile memory; and
determining if said cache off load has been completed.

### Claim 6 (depends on 5)

The method of claim 5, further comprising
ensuring that said cache offload can be completed;
invalidating a universal serial bus flash image so that a new cache offload can take place;
flushing data from a cache; and
continuing said redundant array of independent drives controller in normal operation.

### Claim 7

A controller board device comprising:
a host peripheral component interconnect express connector unit;
a redundant array of independent drives in communication with said host peripheral component interconnect express connector unit;
a flash drive in communication with said redundant array of independent drives; and
an alternate power supply in communication with said redundant array of independent drives.

### Claim 8 (depends on 7)

The controller board of claim 7, further comprising:
at least two power rails transmitted from said host peripheral component interconnect express connector unit to said redundant array of independent drives controller.

### Claim 9 (depends on 8)

The controller board of claim 8, wherein said at least two power rails comprise a 3.3 volt power rail and a 12 volt power rail.

### Claim 10 (depends on 9)

The controller board of claim 9, wherein said 3.3 volt power rail is transmitted from said host peripheral component interconnect express connector unit to a 3.3 volt power protection unit and said 12 volt power rail is transmitted from said host peripheral component interconnect express connector unit to a 12 volt power protection unit, wherein said 13 volt power rail and said 12 volt power rail are transmitted from said 3.3 volt power protection unit and said 12 volt power protection unit to said redundant array of independent drives controller.

### Claim 11 (depends on 10)

The controller board of claim 10, wherein said 3.3 volt power rail and said 12 volt power rail are each monitored by a dual power supply monitor, wherein said dual power supply monitor is in communication with a power loss pin operably linked to said redundant array of independent drives controller.

### Claim 12 (depends on 11)

The controller board of claim 11, wherein said alternate power source transmits at least two power rails to said redundant array of independent drive.

### Claim 13 (depends on 12)

The controller board of claim 12, wherein said at least two power rails from said alternate power source to said redundant array of independent drives comprise said 3.3 volt power rail and said 12 volt power rail.

### Claim 14 (depends on 13)

The controller board of claim 13, wherein said redundant array of independent drives controller is in communication with a reset logic block, wherein said reset logic block is in communication with a delay block.

### Claim 15 (depends on 14)

The controller board of claim 14, wherein said flash block is in communication with said redundant array of independent drives controller by means of a USB Phy and Flash controller.