# US 2014/0195716 A1 · Method And Apparatus For Dynamically Allocating Memory Address Space Between Physical Memories > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0195716 A1 - Document ID: US20140195716A1 - Status: Published application - Kind: A1 - Application number: 13/738,709 - Filed: 2013-01-10 - Published: 2014-07-10 - Earliest claimed: 2013-01-10 - Assignees: Avnera Corporation - Applicants: Avnera Corporation - Inventors: Ole Bentz; Robert Mays; Bruce Nepple; James Anderson - Web page: https://patentgrep.com/patent/US20140195716A1 ## CPC - G06F 12/0223: {User address space allocation, e.g. contiguous or non contiguous base addressing} - G06F 12/0638: {Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module (address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70)} - G06F 2212/1012: Design facilitation - G06F 2212/205: Hybrid memory, e.g. using both volatile and non-volatile memory - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory address space for each of a plurality of physical memories in a microprocessor-based system is allocated prior to knowing the desired logical size of at least one of the physical memories. At least two of the allocated memory address spaces overlap at least a portion of each other. After the system is fabricated, a pointer value set that corresponds to an address boundary between at least two physical memories of the fabricated system is set during boot time and/or during run time when the size of the physical memories are known. The technique provides a faster time-to-market for microprocessor-based systems by allowing, for example, Application Specific Integrated Circuits (ASICs) comprising microprocessor systems on-chip be manufactured prior to the final firmware and software being fully developed. Additionally, the subject matter disclosed herein permits changes in memory-space allocation for finalized ASIC designs. ## Claims ### Claim 1 A method, comprising: allocating a memory address space for each of a plurality of physical memories in a microprocessor-based system, a size of at least one physical memory being unknown at a time the memory address space for the at least one physical memory is allocated and at least two of the allocated memory address spaces overlapping at least a portion of each other; fabricating the system; and setting a pointer value corresponding to an address boundary between at least two physical memories of the fabricated system, the size of the at least one physical memory being known at a time the pointer is set. ### Claim 2 (depends on 1) The method according to claim 1, wherein setting the pointer comprises setting the pointer at a boot time of the system based on the size of the at least one physical memory being known at a time the pointer is set. ### Claim 3 (depends on 2) The method according to claim 2, wherein setting the pointer further comprises setting the pointer during a run time of the system after the boot time of the system. ### Claim 4 (depends on 1) The method according to claim 1, wherein setting the pointer comprises setting the pointer during a run time of the system after a boot time of the system. ### Claim 5 (depends on 1) The method according to claim 1, wherein the plurality of physical memories comprises at least one Read Only Memory (ROM) and at least one Random Access Memory (RAM). ### Claim 6 (depends on 1) The method according to claim 1, wherein the plurality of physical memories comprises at least one Read Only Memory (ROM) and a plurality of Random Access Memories (RAMs), the method further comprising setting a second pointer corresponding to a RAM of the plurality of RAMs selected to be active. ### Claim 7 (depends on 1) The method according to claim 1, wherein the system comprising a microprocessor-based Application Specific Integrated Circuit (ASIC). ### Claim 8 (depends on 7) The method according to claim 7, wherein the ASIC is part of an information-handling system. ### Claim 9 (depends on 8) The method according to claim 8, wherein the information-handling system comprises a touch-screen display. ### Claim 10 (depends on 9) The method according to claim 9, wherein the information-handling system comprises a wireless link interface. ### Claim 11 (depends on 8) The method according to claim 8, wherein the information-handling system comprises a wireless link interface. ### Claim 12 A method, comprising: defining a memory space for a system; allocating a memory address space for each of a plurality of physical memories in the system, a size of at least one physical memory being unknown at a time the memory address space for the at least one physical memory is allocated and at least two of the allocated memory address spaces overlapping at least a portion of each other; fabricating the system; and setting a pointer value corresponding to an address boundary between at least two physical memories of the fabricated system, the size of the at least one physical memory being known at a time the pointer is set. ### Claim 13 (depends on 12) The method according to claim 12, wherein setting the pointer comprises setting the pointer at a boot time of the system based on the size of the at least one physical memory being known at a time the pointer is set. ### Claim 14 (depends on 13) The method according to claim 13, wherein setting the pointer further comprises setting the pointer during a run time of the system after the boot time of the system. ### Claim 15 (depends on 12) The method according to claim 12, wherein setting the pointer comprises setting the pointer during a run time of the system after a boot time of the system. ### Claim 16 (depends on 12) The method according to claim 12, wherein the plurality of physical memories comprises at least one Read Only Memory (ROM) and at least one Random Access Memory (RAM). ### Claim 17 (depends on 12) The method according to claim 12, wherein the plurality of physical memories comprises at least one Read Only Memory (ROM) and a plurality of Random Access Memories (RAMs), the method further comprising setting a second pointer corresponding to a RAM of the plurality of RAMs selected to be active. ### Claim 18 (depends on 12) The method according to claim 12, wherein the system comprising a microprocessor-based Application Specific Integrated Circuit (ASIC). ### Claim 19 (depends on 18) The method according to claim 18, wherein the ASIC is part of an information-handling system. ### Claim 20 (depends on 19) The method according to claim 19, wherein the information-handling system comprises a touch-screen display.