# US 2014/0195715 A1 · Scalable memory system

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- Number: US 2014/0195715 A1
- Document ID: US20140195715A1
- Status: Published application
- Kind: A1
- Application number: 14/172,946
- Filed: 2014-02-05
- Published: 2014-07-10
- Earliest claimed: 2006-08-22
- Assignees: Mosaid Technologies Incorporated
- Applicants: Mosaid Technologies Incorporated
- Inventors: Jin-Ki KIM; HakJune OH; Hong Beom PYEON; Steven PRZYBYLSKI
- Web page: https://patentgrep.com/patent/US20140195715A1

## CPC

- G11C 7/1042: {using interleaving techniques, i.e. read-write of one part of the memory while preparing another part}
- G06F 12/0623: {for memory modules}
- G06F 13/1694: {Configuration of memory controller to different memory types}
- G06F 13/4256: {using a clocked protocol}
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 16/10: Programming or data input circuits
- G11C 16/06: Auxiliary circuits, e.g. for writing into memory
- G11C 2216/30: Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.

## Claims

### Claim 1

A method comprising:
receiving, at a memory device of a memory system having serially connected memory devices, a first command including a device address corresponding to the memory device;
executing at least one core operation in a first memory bank of the memory device in response to the first command;
receiving, at the memory device, a second command during execution of the at least one core operation in the first memory bank, the second command including the device address corresponding to the memory device; and,
executing, concurrently with the execution of one or more of the at least one core operation executed in the first memory bank, at least one core operation in a second memory bank of the selected memory device in response to the second command.

### Claim 2 (depends on 1)

The method of claim 1, further including
receiving a third command for requesting result information from one of the first memory bank and the second memory bank, and
outputting a read data packet containing the result information in response to the third command.

### Claim 3 (depends on 2)

The method of claim 2, wherein the result information includes one of status register data and read data.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first command and the second command are command packets including a series of bits logically configured to include:
a mandatory command field for providing an operation code and a device address,
an optional address field following the command field for providing one of a row and column address when the operation code corresponds to a read or write operation, and,
an optional data field following the address field for providing write data when the operation code corresponds to the write operation.

### Claim 5 (depends on 4)

The method of claim 4, wherein
a first command strobe is received in parallel with the first command, the first command strobe having an active duration corresponding to the length of the first command, and
a second command strobe is received in parallel with the second command, the second command strobe having an active duration corresponding to the length of the second command.

### Claim 6 (depends on 5)

The method of claim 5, wherein a data input strobe is received for enabling outputting of the read data packet while the data input strobe is at the active level.

### Claim 7 (depends on 6)

The method of claim 6, wherein the first command strobe and the second command strobe are separated by at least one data latching clock edge.

### Claim 8 (depends on 6)

The method of claim 6, wherein the second command strobe and data input strobe are separated by at least one data latching clock edge.

### Claim 9 (depends on 1)

The method of claim 1, further comprising initializing the memory device by generating device address and device identifier information for the memory device.

### Claim 10

A memory device configured to:
receive a first command including a device address corresponding to the memory device;
execute at least one core operation in a first memory bank of the memory device in response to the first command;
receive a second command during execution of the at least one core operation in the first memory bank, the second command including the device address corresponding to the memory device; and
execute, concurrently with the execution of one or more of the at least one core operation executed in the first memory bank, at least one core operation in a second memory bank of the selected memory device in response to the second command.

### Claim 11 (depends on 10)

The memory device of claim 10, further configured to:
receive a third command for requesting result information from one of the first memory bank and the second memory bank, and
output a read data packet containing the result information in response to the third command.

### Claim 12 (depends on 11)

The memory device of claim 11, wherein the result information includes one of status register data and read data.

### Claim 13 (depends on 10)

The memory device of claim 10, wherein the first command and the second command are command packets including a series of bits logically configured to include:
a mandatory command field for providing an operation code and a device address,
an optional address field following the command field for providing one of a row and column address when the operation code corresponds to a read or write operation, and,
an optional data field following the address field for providing write data when the operation code corresponds to the write operation.

### Claim 14 (depends on 13)

The memory device of claim 13, wherein:
a first command strobe is received in parallel with the first command, the first command strobe having an active duration corresponding to the length of the first command, and
a second command strobe is received in parallel with the second command, the second command strobe having an active duration corresponding to the length of the second command.

### Claim 15 (depends on 14)

The memory device of claim 14, wherein a data input strobe is received for enabling outputting of the read data packet while the data input strobe is at the active level.

### Claim 16 (depends on 15)

The memory device of claim 15, wherein the first command strobe and the second command strobe are separated by at least one data latching clock edge.

### Claim 17 (depends on 15)

The memory device of claim 15, wherein the second command strobe and data input strobe are separated by at least one data latching clock edge.

### Claim 18 (depends on 10)

The memory device of claim 10, further comprising initializing the memory device by generating device address and device identifier information for the memory device.

### Claim 19

A memory system having serially connected memory devices, wherein at least one of the memory devices is configured to:
receive a first command including a device address corresponding to the at least one memory device;
execute at least one core operation in a first memory bank of the memory device in response to the first command;
receive a second command during execution of the at least one core operation in the first memory bank, the second command including the device address corresponding to the at least one memory device; and
execute, concurrently with the execution of one or more of the at least one core operation executed in the first memory bank, at least one core operation in a second memory bank of the selected memory device in response to the second command.