# US 2014/0195702 A1 · Method of operating data compression circuit and devices to perform the same

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- Number: US 2014/0195702 A1
- Document ID: US20140195702A1
- Status: Published application
- Kind: A1
- Application number: 14/146,846
- Filed: 2014-01-03
- Published: 2014-07-10
- Earliest claimed: 2013-01-07
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd
- Inventors: Man Keun SEO; Dae Wook KIM; Hong Rak SON; Jun Jin KONG
- Web page: https://patentgrep.com/patent/US20140195702A1

## CPC

- H03M 7/30: Compression (speech analysis-synthesis for redundancy reduction G10L19/00; for image communication H04N); Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- G06F 13/14: Handling requests for interconnection or transfer
- G06F 13/1668: {Details of memory controller}
- H03M 7/3084: {using adaptive string matching, e.g. the Lempel-Ziv method}
- H03M 7/3091: {Data deduplication}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method of operating a data compression circuit includes receiving and storing a plurality of data blocks until a cache is full and writing the data blocks that have been stored in the cache to a buffer memory when the cache is full. The method also includes performing forced literal/literal encoding on each of the data blocks regardless of repetitiveness of each data block when the cache is full.

## Claims

### Claim 1

A method of operating a data compression circuit, the method comprising:
receiving and storing a plurality of data blocks until a cache is full; and
writing the data blocks, which have been stored in the cache, to a buffer memory when the cache is full.

### Claim 2 (depends on 1)

The method of claim 1, further comprising performing forced encoding on each of the data blocks regardless of repetitiveness of each data block when the cache is full.

### Claim 3 (depends on 1)

The method of claim 1, wherein a size of the cache is determined by a size of data that is able to be written to the buffer memory during a single cycle.

### Claim 4 (depends on 1)

The method of claim 1, wherein the writing the data blocks comprises writing each of the data blocks to one of a plurality of memories respectively having addresses allocated using an interleaving method, wherein the buffer memory includes the plurality of the memories.

### Claim 5 (depends on 4)

The method of claim 4, wherein each of the memories is a single-port static random access memory (SRAM).

### Claim 6

A data compression circuit, comprising:
a cache to receive and store a plurality of data blocks;
a buffer memory to receive and store the data blocks output from the cache when the cache is full; and
a compressed-data generation circuit to perform forced encoding on each of the data blocks regardless of repetitiveness of each data block.

### Claim 7 (depends on 6)

The data compression circuit of claim 6, wherein a size of the cache is determined by a size of data that is able to be written to the buffer memory during a single cycle.

### Claim 8 (depends on 6)

The data compression circuit of claim 6, wherein the buffer memory comprises a plurality of memories respectively having addresses allocated in an interleaving method to respectively store the data blocks, and each of the memories is a single-port static random access memory (SRAM).

### Claim at position 9

9-10. (canceled)

### Claim 11

A method of operating a data compression circuit, the method comprising:
reading a plurality of reference data blocks neighboring each other from a buffer memory simultaneously based on an address;
comparing one of the reference data blocks with a data block; and
encoding the data block based on a result of the comparison.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
comparing another one of the reference data blocks with a subsequent data block following the data block; and
encoding the subsequent data block based on a result of the comparison.

### Claim 13 (depends on 12)

The method of claim 12, wherein the encoding comprises performing one of literal/literal encoding and length/distance encoding on the subsequent data block.

### Claim 14 (depends on 11)

The method of claim 11, wherein the reading the reference data blocks simultaneously comprises simultaneously reading the reference data blocks from a plurality of memories, which respectively have addresses allocated using an interleaving method, based on the address.

### Claim 15

A data processing system, comprising:
a host to generate an input data stream including a plurality of data blocks; and
a memory controller to transmit and receive the input data stream from the host, the memory controller comprising a data compression circuit that comprises:
a cache to receive and store the plurality of data blocks,
a buffer memory to store the plurality of data blocks within a plurality of internal memories when the cache is full such that the plurality of data blocks are each to be used as a plurality of reference data blocks to determine whether another data block to be processed is a repetition of one of the reference data blocks, and
a compressed-data generation circuit to perform one of a plurality of types of encoding on the another data block based on the determination.

### Claim 16 (depends on 15)

The data processing system of claim 15, wherein:
the buffer memory performs literal/literal encoding by writing the another data block to one of the plurality of internal memories if the another data block to be processed is not a repetition of one of the reference data blocks; and
the buffer memory performs length/distance encoding by reading the another data block and a repetitive data block from one of the plurality of internal memories and writing the another data block to another one of the plurality of internal memories if the another data block to be processed is a repetition of one of the reference data blocks.

### Claim 17 (depends on 15)

The data processing system of claim 15, wherein the data compression circuit further comprises:
an input data register to receive the input data stream, to adjust the delay of each of the plurality data blocks included in the input data stream using delay circuits, and to generate a plurality of delay-adjusted data blocks;
a cache controller to receive the input data stream and to control write operations and read operations of the cache;
a comparison circuit to receive a second of the plurality of delay-adjusted data blocks and to determine whether the another data block is the same as the reference data block; and
a buffer memory controller to receive a first of the plurality of delay-adjusted data blocks and to control at least one of an operation of writing a data block output from the cache to the buffer memory, to control an operation of writing the first delayed data block output from the input data register to the buffer memory, and an operation of transmitting a reference data block output from the buffer memory to the comparison circuit.

### Claim 18 (depends on 17)

The data processing system of claim 17, wherein the input data register transmits a third delayed data block to the compressed-data generation circuit such that comparison circuit compares the reference data block output from the buffer memory controller with the second delayed data block output from the input data register and outputs an indicator indicating whether the another data block is the same as the reference data block, in order to allow the compressed-data generation circuit to perform literal/literal encoding or length/distance encoding on the third delayed data block output from the input data register in response to the indicator.

### Claim 19 (depends on 15)

The data processing system of claim 15, wherein the plurality of internal memories each has a memory area corresponding to an address allocated using an interleaving method to store one of the plurality of data blocks.

### Claim 20 (depends on 15)

The data processing system of claim 15, wherein the memory controller further comprises:
a host interface to transmit the input data stream from the host to the memory controller during a data compression operation and to transmit a decompressed data stream from the memory controller to the host during a data decompression operation.

### Claim 21 (depends on 20)

The data processing system of claim 20, wherein the memory controller further comprises:
at least one data transmission controller to transmit data between the memory controller and at least one external storage device according to an interface protocol of the at least one external storage device; and
a data decompression circuit to receive the data from the at least one external storage device to perform the data decompression operation on the received data.