# US 2014/0195701 A1 · Time-sharing buffer access system

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- Number: US 2014/0195701 A1
- Document ID: US20140195701A1
- Status: Published application
- Kind: A1
- Application number: 13/738,373
- Filed: 2013-01-10
- Published: 2014-07-10
- Earliest claimed: 2013-01-10
- Assignees: Skymedi Corporation
- Applicants: Skymedi Corporation
- Inventors: Ting Wei Chen; HSINGHO LIU; CHUANG CHENG
- Web page: https://patentgrep.com/patent/US20140195701A1

## CPC

- G06F 3/0656: {Data buffering arrangements}
- G06F 13/1663: {Access to shared memory}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A time-sharing buffer access system manages a buffer among plural master devices. Plural buffer handling units are operable to associatively couple the master devices, respectively, and a first end of each buffer handling unit is used to independently transfer data to or from the associated master device. A second end of each buffer handling unit is coupled to a buffer switch. A time slot controller defines a time slot, during which one of the buffer handling units is selected by the buffer switch such that data are only transferred between the selected buffer handling unit and the buffer.

## Claims

### Claim 1

A time-sharing buffer access system for managing a buffer among a plurality of master devices, the system comprising:
a plurality of buffer handling units operable to associatively couple the master devices, respectively, a first end of each said buffer handling unit being used to independently transfer data to or from the associated master device;
a buffer switch, to which a second end of each said buffer handling unit is coupled; and
a time slot controller configured to define a time slot, during which one of the buffer handling units is selected by the buffer switch such that data are only transferred between the selected buffer handling unit and the buffer.

### Claim 2 (depends on 1)

The system of claim 1, wherein the buffer comprises a static random-access memory (SRAM).

### Claim 3 (depends on 1)

The system of claim 1, wherein one or more time slots are allocated exclusively for the master devices in turn.

### Claim 4 (depends on 1)

The system of claim 1, wherein the time slot controller comprises a counter.

### Claim 5 (depends on 1)

The system of claim 1, wherein the buffer handling unit comprises:
a data transfer unit configured to establish a communication channel, at the first end, with the associated master device;
a transfer switch; and
a transfer buffer including a plurality of data blocks, one of which is selected by the transfer switch such that data are transferred, via the transfer switch, between the transfer buffer and the data transfer unit, the transfer buffer being operable, at the second end, to couple the buffer switch via a transfer bus.

### Claim 6 (depends on 5)

The system of claim 5, wherein the data transfer unit establishes the communication channel by handshaking with the associated master device.

### Claim 7 (depends on 5)

The system of claim 5, wherein a time period is divided to N time slots, and data width on the transfer bus is N times data width on the communication channel.

### Claim 8

A memory controller, comprising:
a front-end device configured. to communicate with a host;
a back-end device configured to communicate with a non-volatile memory;
a central processing unit (CPU);
a buffer operable to be accessed among the front-end device, the back-end device and the CPU; and
a time-sharing buffer access system configured to simultaneously transfer data to or from the front-end device, the back-end device and the CPU, and to allocate dedicated time slots respectively and exclusively for the front-end device, the back-end device and the CPU in turn, for transferring data between the time-sharing buffer system and the buffer.

### Claim 9 (depends on 8)

The memory controller of claim 8, wherein the buffer comprises a static random-access memory (SRAM).

### Claim 10 (depends on 8)

The memory controller of claim 8, wherein one or more time slots are allocated exclusively for the front-end device, the back-end device and the CPU in turn.

### Claim 11 (depends on 8)

The memory controller of claim 8, wherein the time-sharing buffer access system comprises:
a plurality of buffer handling units operable to associatively couple the front-end device, the back-end device and the CPU, respectively, a first end of each said buffer handling unit being used to independently transfer data to or from the associated front-end device, the back-end device or the CPU;
a buffer switch, to which a second end of each said buffer handling unit is coupled; and
a time slot controller configured to define a time slot, during which one of the buffer handling units is selected by the buffer switch such that data are only transferred between the selected buffer handling unit and the buffer.

### Claim 12 (depends on 11)

The memory controller of claim 11, wherein, the buffer handling unit comprises:
a data transfer unit configured to establish a communication channel, at the first end, with the associated front-end device, the back-end device or the CPU;
a transfer switch; and
a transfer buffer including a plurality of data blocks, one of which is selected by the transfer switch such that data are transferred, via the transfer switch, between the transfer buffer and the data transfer unit, the transfer buffer being operable, at the second end, to couple the buffer switch via a transfer bus.

### Claim 13 (depends on 12)

The memory controller of claim 12, wherein the data transfer unit establishes the communication channel by handshaking with the associated front-end device, the back-end device or the CPU.

### Claim 14 (depends on 12)

The memory controller of claim 12, wherein a time period is divided to N time slots, and data width on the transfer bus is N times data width on the communication channel.

### Claim 15 (depends on 11)

The memory controller of claim 11, wherein the time slot controller comprises a counter.