Fixed point division circuit utilizing floating point architecture

Abstract

A system, method, and computer program product for dividing two binary numbers. The divider implements a fixed point division function using a floating point normalization architecture to yield the closest initial quotient approximation. The divider normalizes the input dividend and divisor to a range of [0.5, 1.0) by scaling each by necessary factors of two. The normalized inputs are submitted to a divider core that may be optimized for dividing inputs of such limited ranges. The divider core output is then rescaled by an appropriate factor of two, appropriately signed, and loaded into saturating registers for output in various formats. The divider core progressively outputs quotient bits in decreasing order of significance until a predetermined level of precision is reached, typically fewer bits than in a complete quotient, for faster output. One embodiment generates the six most significant quotient bits in one clock cycle.

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