# US 2014/0195196 A1 · Chip performance monitoring system and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0195196 A1 - Document ID: US20140195196A1 - Status: Published application - Kind: A1 - Application number: 13/737,168 - Filed: 2013-01-09 - Published: 2014-07-10 - Earliest claimed: 2013-01-09 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Margaret R. Charlebois; Christopher D. Hanudel; Robert D. Herzl; David W. Milton; Clarence R. Ogilvie; Paul M. Schanely; Tad J. Wilder - Web page: https://patentgrep.com/patent/US20140195196A1 ## CPC - G01R 31/3177: Testing of logic operation, e.g. by logic analysers - G01R 31/31727: {Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922)} - G01R 31/318577: {AC testing, e.g. current testing, burn-in} - G06F 1/08: Clock generators with changeable or programmable clock frequency - G06F 11/348: {Circuit details, i.e. tracer hardware} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Disclosed are a chip performance monitoring system, method and a computer program product, wherein a performance monitor output signal is propagated through an adjacent scan chain to avoid signal degradation incident to across-chip transmission of high frequency signals. Since the clock signal frequency used to control signal propagation through the scan chain will typically be less than twice the performance monitor output signal frequency, frequency sub-sampling with aliasing occurs. To compensate, signal propagation through the scan chain can be controlled during different time periods using different clock signals having different clock signal frequencies and, during these different time periods, different data outputs can be captured at an output node of the scan chain. The data output frequencies of these different data outputs can be measured and the performance monitor output signal frequency can be determined based on the different data output frequencies given the different clock signal frequencies. ## Claims ### Claim 1 A chip performance monitoring system comprising: a performance monitor on an integrated circuit chip and outputting a performance monitor output signal having a performance monitor output signal frequency; a scan chain on said chip; and a multiplexer on said chip electrically connected between said performance monitor and an input node of said scan chain, said multiplexer selectively applying said performance monitor output signal to said input node and said scan chain propagating said performance monitor output signal. ### Claim 2 (depends on 1) The chip performance monitoring system of claim 1, further comprising a variable clock signal generator generating different clock signals having different clock signal frequencies for controlling signal propagation timing through said scan chain within different time periods such that, during said different time periods, different data outputs with different data output frequencies are output at an output node of said scan chain, said different clock signal frequencies each being less than twice said performance monitor output signal frequency. ### Claim 3 (depends on 2) The chip performance monitoring system of claim 2, further comprising a processor electrically connected to said output node, said processor measuring said different data output frequencies of said different data outputs at said output node during said different time periods and determining said performance monitor output signal frequency based on said different data output frequencies given said different clock signal frequencies. ### Claim 4 (depends on 3) The chip performance monitoring system of claim 3, said processor comprising any one of an on-chip processor electrically connected directly to said output node and an off-chip processor electrically connected to said output node through an output pin. ### Claim 5 (depends on 1) The chip performance monitoring system of claim 1, said performance monitor comprising a ring oscillator. ### Claim 6 (depends on 1) The chip performance monitoring system of claim 1, said scan chain comprising a plurality of multiplexed flip-flops connected in series, said input node being connected to a first multiplexed flip-flop in said scan chain, and said multiplexer selectively applying one of said performance monitor output signal and scan data from a test pattern generator to said input node. ### Claim 7 (depends on 1) The chip performance monitoring system of claim 1, said scan chain comprising a plurality of multiplexed flip-flops connected in series, said input node being connected to one of an intermediate multiplexed flip-flop and a last flip-flop in said scan chain and said multiplexer selectively applying one of said performance monitor output signal and scan data from an immediately preceding multiplexed flip-flop in said scan chain to said input node. ### Claim 8 (depends on 2) The chip performance monitoring system of claim 2, said scan chain comprising a plurality of multiplexed flip-flops connected in series and said output node being connected to any one of an intermediate multiplexed flip-flop in said scan chain downstream of said input node and a last multiplexed flip-flop in said scan chain. ### Claim 9 A chip performance monitoring system comprising: a performance monitor on an integrated circuit chip and outputting a performance monitor output signal having a performance monitor output signal frequency; a scan chain on said chip; a multiplexer electrically connected between said performance monitor and an input node of said scan chain, said multiplexer selectively applying said performance monitor output signal to said input node and said scan chain propagating said performance monitor output signal; a variable clock signal generator on said chip and generating different clock signals having different clock signal frequencies for controlling signal propagation timing through said scan chain within different time periods such that, during said different time periods, different data outputs with different data output frequencies are output at an output node of said scan chain, said different clock signal frequencies each being less than twice said performance monitor output signal frequency; and a processor electrically connected to said output node, said processor measuring said different data output frequencies of said different data outputs at said output node during said different time periods and determining said performance monitor output signal frequency based on said different data output frequencies given said different clock signal frequencies. ### Claim 10 (depends on 9) The chip performance monitoring system of claim 9, said different clock signals comprising at least two different clock signals with at least two different clock signal frequencies, respectively. ### Claim 11 (depends on 9) The chip performance monitoring system of claim 9, said processor comprising any one of an on-chip processor electrically connected directly to said output node and an off-chip processor electrically connected to said output node through an output pin. ### Claim 12 (depends on 9) The chip performance monitoring system of claim 9, said performance monitor comprising a ring oscillator. ### Claim 13 (depends on 9) The chip performance monitoring system of claim 9, said scan chain comprising a plurality of multiplexed flip-flops connected in series, said input node being connected to a first multiplexed flip-flop in said scan chain, and said multiplexer selectively applying one of said performance monitor output signal and scan data from a test pattern generator to said input node. ### Claim 14 (depends on 9) The chip performance monitoring system of claim 9, said scan chain comprising a plurality of multiplexed flip-flops connected in series, said input node being connected to one of an intermediate multiplexed flip-flop and a last flip-flop in said scan chain and said multiplexer selectively applying one of said performance monitor output signal and scan data from an immediately preceding multiplexed flip-flop in said scan chain to said input node. ### Claim 15 (depends on 9) The chip performance monitoring system of claim 9, said scan chain comprising a plurality of multiplexed flip-flops connected in series and said output node being connected to any one of an intermediate multiplexed flip-flop in said scan chain downstream of said input node and a last multiplexed flip-flop in said scan chain. ### Claim 16 A chip performance monitoring method comprising: receiving, by a processor, different data outputs captured at an output node of a scan chain on an integrated circuit chip at different time periods during propagation of a performance monitor output signal through said scan chain from an input node and to said output node, said different time periods corresponding to when timing of said propagation is controlled by different clock signals having different clock signal frequencies; determining, by said processor, different data output frequencies of said different data outputs; and determining, by said processor, a performance monitor output signal frequency of said performance monitor output signal based on said different data output frequencies given said different clock signal frequencies. ### Claim 17 (depends on 16) The chip performance monitoring method of claim 16, said different clock signals comprising at least two different clock signals with at least two different clock signal frequencies, respectively. ### Claim 18 (depends on 16) The chip performance monitoring method of claim 16, said determining of said performance monitor output signal frequency based on said different clock signal frequencies and said different data output frequencies comprising: plotting, on a graph, a first horizontal line and a second horizontal line, said first horizontal line representing a first data output frequency of a first data output captured at said output node during a first time period and associated with a first clock signal having a first clock signal frequency and said second horizontal line representing a second data output frequency of a second data output captured at said output node during a second time period and associated with a second clock signal having a second clock signal frequency; plotting, on said graph, a first triangular wave and a second triangular wave, said first triangular wave representing first possible performance monitor output signal frequency values given said first clock signal frequency and said first data output frequency and said second triangular wave representing second possible performance monitor output signal frequency values given said second clock signal frequency and said second data output frequency; and analyzing said graph to identify said performance monitor output signal frequency as a common frequency where said first triangular wave intersects said first horizontal line and said second triangular wave intersects said second horizontal line. ### Claim 19 (depends on 18) The chip performance monitoring method of claim 18, said method further comprising pre-selecting said first clock signal frequency and said second clock signal frequency so that a pattern created by said first horizontal line, said second horizontal line, said first triangular wave and said second triangular wave is non-repeating within a given range of possible performance monitor output signals so as to ensure that only one common frequency is identified as said performance monitor output signal frequency. ### Claim 20 (depends on 19) The chip performance monitoring method of claim 19, said pre-selecting further being performed so that said first data output frequency and said second data output frequency are between high and low peaks of both said first triangular wave and said second triangular wave. ### Claim 21 (depends on 16) The chip performance monitoring method of claim 16, said performance monitor comprising a ring oscillator. ### Claim 22 (depends on 16) The chip performance monitoring method of claim 16, said scan chain comprising a plurality of multiplexed flip-flops connected in series, said input node being connected to a first multiplexed flip-flop in said scan chain, and said multiplexer selectively applying one of said performance monitor output signal and scan data from a test pattern generator to said input node. ### Claim 23 (depends on 16) The chip performance monitoring method of claim 16, said scan chain comprising a plurality of multiplexed flip-flops connected in series, said input node being connected to one of an intermediate multiplexed flip-flop and a last flip-flop in said scan chain and said multiplexer selectively applying one of said performance monitor output signal and scan data from an immediately preceding multiplexed flip-flop in said scan chain to said input node. ### Claim 24 (depends on 16) The chip performance monitoring method of claim 16, said scan chain comprising a plurality of multiplexed flip-flops connected in series and said output node being connected to any one of an intermediate multiplexed flip-flop in said scan chain downstream of said input node and a last multiplexed flip-flop in said scan chain. ### Claim 25 A computer program product comprising a tangible computer readable storage device, said tangible computer readable storage device storing program code, said program code being executable by a computer to perform a chip performance monitoring method, said chip performance monitoring method comprising: receiving different data outputs captured at an output node of a scan chain on an integrated circuit chip at different time periods during propagation of a performance monitor output signal through said scan chain from an input node to said output node, said different time periods corresponding to when timing of said propagation is controlled by different clock signals having different clock signal frequencies; determining different data output frequencies of said different data outputs; and determining a performance monitor output signal frequency of said performance monitor output signal based on said different data output frequencies given said different clock signal frequencies.