# US 2014/0195175 A1 · Measuring dielectric breakdown in a dynamic mode

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- Number: US 2014/0195175 A1
- Document ID: US20140195175A1
- Status: Published application
- Kind: A1
- Application number: 13/734,075
- Filed: 2013-01-04
- Published: 2014-07-10
- Earliest claimed: 2013-01-04
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Eduard A. Cartier; Charles LaRow; Travis S. Merrill; Ernest Y. Wu
- Web page: https://patentgrep.com/patent/US20140195175A1

## CPC

- G06F 17/10: Complex mathematical operations {(function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544)}
- G01R 31/129: {of components or parts made of semiconducting materials; of LV components or parts (G01R31/18 takes precedence)}
- G01R 31/3008: {Quiescent current [IDDQ] test or leakage current test}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

Embodiments of the present invention provide a method, system, and program product for testing a semiconductor device to measure dielectric breakdown. A computer applies a plurality of stress voltages to a semiconductor device under test. The computer determines a plurality of current measurements until a failure criteria occurs, using a predefined voltage ramp rate and a predefined plurality of stress voltage steps, wherein the number of the plurality of current measurements is less than or equal to the number of the predefined plurality of voltage steps. The computer identifies a stress voltage at which the semiconductor device fails. The computer calculates a frequency dependent voltage acceleration factor based on the quotient of the natural log of the voltage at which the semiconductor device under test failed to the natural log of the predetermined voltage ramp rate.

## Claims

### Claim 1

A method for testing a semiconductor device to measure dielectric breakdown, comprising:
a computer applying a plurality of stress voltages to a semiconductor device under test;
the computer determining a plurality of current measurements until a failure criteria occurs, using a predefined voltage ramp rate and a predefined plurality of stress voltage steps, wherein the number of the plurality of current measurements is less than or equal to the number of the predefined plurality of voltage steps;
the computer identifying a stress voltage at which the semiconductor device fails; and
the computer calculating a frequency dependent voltage acceleration factor based on the quotient of the natural log of the voltage at which the semiconductor device under test failed to the natural log of the predetermined voltage ramp rate.

### Claim 2 (depends on 1)

The method of claim 1, wherein the predefined voltage ramp rate is defined as R (rate)=dVi/dt, wherein V, is a stress voltage in the plurality of stress voltages, and wherein t is the duration of the stress voltage.

### Claim 3 (depends on 1)

The method of claim 1, wherein the determining the plurality of current measurements includes determining a current and identifying a voltage at each step included in the predefined plurality of voltage steps.

### Claim 4 (depends on 1)

The method of claim 1, wherein the plurality of stress voltages produces alternating current, direct current, or both.

### Claim 5 (depends on 4)

The method of claim 4, wherein the failure criteria includes at least one of the following:
the applied stress voltage being greater than or equal to a predetermined maximum voltage;
a measured current of the plurality of current measurements being greater than or equal to a predetermined maximum current; or
a logarithmic slope of a current versus a voltage curve, derived from the plurality of current measurements and the plurality of stress voltages, increases by a factor two to fives times greater than or equal to a previously calculated logarithmic slope included in the current versus the voltage curve or a predetermined slope.

### Claim 6 (depends on 1)

The method of claim 1, wherein the frequency dependent voltage acceleration factor is defined by the following formula: n={Ln(VFAIL)/LnR}−1, wherein VFAIL is the stress voltage at which the semiconductor device fails, and wherein R is the predefined voltage ramp rate.

### Claim 7

A computer system for testing a semiconductor device to measure dielectric breakdown, the computer system comprising:
one or more processors, one or more computer-readable memories, one or more computer-readable storage devices, and program instructions stored on at least one of the one or more storage devices for execution by at least one of the one or more processors via at least one of the one or more memories, the program instructions comprising:
program instructions to apply a plurality of stress voltages to a semiconductor device under test;
program instructions to determine a plurality of current measurements until a failure criteria occurs, using a predefined voltage ramp rate and a predefined plurality of stress voltage steps, wherein the number of the plurality of current measurements is less than or equal to the number of the predefined plurality of voltage steps;
program instructions to identify a stress voltage at which the semiconductor device fails; and
program instructions to calculate a frequency dependent voltage acceleration factor based on the quotient of the natural log of the voltage at which the semiconductor device under test failed to the natural log of the predetermined voltage ramp rate.

### Claim 8 (depends on 7)

The computer system of claim 7, wherein the predefined voltage ramp rate is defined as R(rate)=dVi/dt, wherein V, is a stress voltage in the plurality of stress voltages, and wherein t is the duration of the stress voltage.

### Claim 9 (depends on 7)

The computer system of claim 7, wherein the determining the plurality of current measurements includes determining a current and identifying a voltage at each step included in the predefined plurality of voltage steps.

### Claim 10 (depends on 7)

The computer system of claim 7, wherein the plurality of stress voltages produces alternating current, direct current, or both.

### Claim 11 (depends on 10)

The computer system of claim 10, wherein the failure criteria includes at least one of the following:
the applied stress voltage being greater than or equal to a predetermined maximum voltage;
a measured current of the plurality of current measurements being greater than or equal to a predetermined maximum current; or
a logarithmic slope of a current versus a voltage curve, derived from the plurality of current measurements and the plurality of stress voltages, increases by a factor two to fives times greater than or equal to a previously calculated logarithmic slope included in the current versus the voltage curve or a predetermined slope.

### Claim 12 (depends on 7)

The computer system of claim 7, wherein the frequency dependent voltage acceleration factor is defined by the following formula: n={Ln(VFAIL)/LnR}−1, wherein VFAIL is the stress voltage at which the semiconductor device fails, and wherein R is the predefined voltage ramp rate.

### Claim 13

A computer program product for testing a semiconductor device to measure dielectric breakdown, the computer program product comprising:
one or more computer-readable storage media and program instructions stored on the one or more computer-readable storage media, the program instructions comprising:
program instructions to apply a plurality of stress voltages to a semiconductor device under test;
program instructions to determine a plurality of current measurements until a failure criteria occurs, using a predefined voltage ramp rate and a predefined plurality of stress voltage steps, wherein the number of the plurality of current measurements is less than or equal to the number of the predefined plurality of voltage steps;
program instructions to identify a stress voltage at which the semiconductor device fails; and
program instructions to calculate a frequency dependent voltage acceleration factor based on the quotient of the natural log of the voltage at which the semiconductor device under test failed to the natural log of the predetermined voltage ramp rate.

### Claim 14 (depends on 13)

The computer program product of claim 13, wherein the predefined voltage ramp rate is defined as R(rate)=dVi/dt, wherein V, is a stress voltage in the plurality of stress voltages, and wherein t is the duration of the stress voltage.

### Claim 15 (depends on 13)

The computer program product of claim 13, wherein the determining the plurality of current measurements includes determining a current and identifying a voltage at each step included in the predefined plurality of voltage steps.

### Claim 16 (depends on 13)

The computer program product of claim 13, wherein the plurality of stress voltages produces alternating current, direct current, or both.

### Claim 17 (depends on 16)

The computer program product of claim 16, wherein the failure criteria includes at least one of the following:
the applied stress voltage being greater than or equal to a predetermined maximum voltage;
a measured current of the plurality of current measurements being greater than or equal to a predetermined maximum current; or
a logarithmic slope of a current versus a voltage curve, derived from the plurality of current measurements and the plurality of stress voltages, increases by a factor two to fives times greater than or equal to a previously calculated logarithmic slope included in the current versus the voltage curve or a predetermined slope.

### Claim 18 (depends on 13)

The computer program product of claim 13, wherein the frequency dependent voltage acceleration factor is defined by the following formula: n={Ln(VFAIL)/LnR}−1, wherein VFAIL is the stress voltage at which the semiconductor device fails, and wherein R is the predefined voltage ramp rate.
