# US 2014/0194081 A1 · Superheterodyne Receiver > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0194081 A1 - Document ID: US20140194081A1 - Status: Published application - Kind: A1 - Application number: 14/145,463 - Filed: 2013-12-31 - Published: 2014-07-10 - Earliest claimed: 2012-06-21 - Assignees: Huawei Technologies Co., Ltd. - Applicants: Huawei Technologies Co., Ltd. - Inventors: Massoud Tohidian; Iman Madadi; Robert Bogdan Staszewski - Web page: https://patentgrep.com/patent/US20140194081A1 ## CPC - H04B 1/26: for superheterodyne receivers (multiple frequency-changing H03D7/16) - H04B 1/0007: {wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage} - H04B: TRANSMISSION ## Abstract The invention relates to a superheterodyne receiver, comprising: a sampling mixer being configured to sample an analog radio frequency signal using a certain sampling rate (fs) to obtain a discrete-time sampled signal, and to shift the discrete-time sampled signal towards a first intermediate frequency (|fRF−fLO|) to obtain an intermediate discrete-time signal sampled at the fs; a discrete-time filter being configured to filter the intermediate discrete-time signal at the fs to obtain a filtered signal; and a discrete-time mixer being configured to shift the filtered signal towards a second intermediate frequency (fIF). ## Claims ### Claim 1 A superheterodyne receiver, comprising: a sampling mixer configured to: sample an analog radio frequency signal using a certain sampling rate (fs) to obtain a discrete-time sampled signal; and shift the discrete-time sampled signal towards a first intermediate frequency (|fRF−fLO|) to obtain an intermediate discrete-time signal sampled at the fs; a discrete-time filter configured to filter the intermediate discrete-time signal at the fs to obtain a filtered signal; and a discrete-time mixer configured to shift the filtered signal towards a second intermediate frequency (fIF). ### Claim 2 (depends on 1) The superheterodyne receiver of claim 1, wherein the fIF is a baseband frequency. ### Claim 3 (depends on 1) The superheterodyne receiver of claim 1, wherein the discrete-time mixer is configured to operate at a decimated sampling rate that is lower than the fs. ### Claim 4 (depends on 1) The superheterodyne receiver of claim 1, wherein the discrete-time mixer is an image-reject mixer. ### Claim 5 (depends on 1) The superheterodyne receiver of claim 1, wherein the discrete-time filter is a low-pass filter. ### Claim 6 (depends on 1) The superheterodyne receiver of claim 1, wherein the discrete-time filter is a band-pass filter. ### Claim 7 (depends on 1) The superheterodyne receiver of claim 1, wherein the discrete-time filter is a complex band-pass filter. ### Claim 8 (depends on 1) The superheterodyne receiver of claim 1, wherein the discrete-time filter is configured to perform a charge sharing between an in-phase and a quadrature-phase component of the intermediate discrete-time signal. ### Claim 9 (depends on 1) The superheterodyne receiver of claim 1, wherein the fs is an oversampling rate with an oversampling factor that is at least 2. ### Claim 10 (depends on 1) The superheterodyne receiver of claim 1, wherein the fs is an oversampling rate with an oversampling factor that is at least 4. ### Claim 11 (depends on 1) The superheterodyne receiver of claim 1, wherein the discrete-time filter comprises a switched capacitor network comprising: an input; an output; a plurality of parallel switched capacitor paths arranged between the input and the output, wherein each switched capacitor path comprises a switched capacitor; and a switch circuitry configured to switch each switched capacitor at a different time instant, thereby outputting a filtered input signal. ### Claim 12 (depends on 11) The superheterodyne receiver of claim 11, wherein the switch circuitry is configured to switch each switched capacitor beginning with a different phase of a common clock signal. ### Claim 13 (depends on 11) The superheterodyne receiver of claim 11, wherein the switch circuitry comprises: a plurality of input switches configured to switch each switched capacitor to the input, thereby charging the switched capacitors; a plurality of output switches configured to switch each switched capacitor to the output, thereby sequentially outputting a plurality of filtered sub-signals collectively representing the filtered input signal; and a plurality of discharge switches, wherein each discharge switch is arranged to switch one of the switched capacitors to a reference potential, thereby discharging the switched capacitor. ### Claim 14 (depends on 1) The superheterodyne receiver of claim 1, wherein the sampling mixer is a quadrature mixer comprising an in-phase path and a quadrature-phase path, wherein the in-phase path is configured to generate an in-phase oscillator signal with the repeating function [1 0 −1 0], and wherein the quadrature-phase path is configured to generate a quadrature-phase oscillator signal with the repeating function [0 1 0 −1]. ### Claim 15 (depends on 1) The superheterodyne receiver of claim 1, wherein the sampling mixer is a quadrature mixer comprising an in-phase path and a quadrature-phase path, wherein the in-phase path is configured to generate an in-phase oscillator signal with the repeating function [1 1+√2 1+°2 1 −1 −1√2 −1−√2 −1], and wherein the quadrature-phase path is configured to generate a quadrature-phase oscillator signal with the repeating function [−1−√2 −1 1 1+√2 1+°2 1 −1 −1−√2]. ### Claim 16 (depends on 1) The superheterodyne receiver of claim 1, wherein the discrete-time mixer comprises a down-sampler configured to provide the filtered signal shifted towards the fIF with a sampling rate reduced towards the fs. ### Claim 17 (depends on 1) The superheterodyne receiver of claim 1, further comprising a converting amplifier configured to convert a voltage signal into a current signal, wherein the converting amplifier is connected to the output of the discrete-time filter. ### Claim 18 (depends on 1) The superheterodyne receiver of claim 1, further comprising a transconductance (gm) stage converting amplifier configured to convert a voltage signal into a current signal, wherein the gm stage converting amplifier is connected to the output of the discrete-time filter. ### Claim 19 (depends on 1) The superheterodyne receiver of claim 1, wherein the discrete-time mixer is a quadrature mixer, and wherein the sampling mixer is a quadrature sampling mixer. ### Claim 20 A superheterodyne receiving method, comprising: sampling an analog radio frequency signal using a certain sampling rate to obtain a discrete-time sampled signal; shifting the discrete-time sampled signal towards a first intermediate frequency to obtain an intermediate discrete-time signal sampled at the certain sampling rate; discrete-time filtering the intermediate discrete-time signal at the certain sampling rate to obtain a filtered signal; and shifting the filtered signal towards a second intermediate frequency. ### Claim 21 An apparatus comprising: at least one processor configured to: sample an analog radio frequency signal using a certain sampling rate to obtain a discrete-time sampled signal; shift the discrete-time sampled signal towards a first intermediate frequency to obtain an intermediate discrete-time signal sampled at the certain sampling rate; discrete-time filter the intermediate discrete-time signal at the certain sampling rate to obtain a filtered signal; and shift the filtered signal towards a second intermediate frequency.