# US 2014/0193974 A1 · Multi-patterning method and device formed by the method

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- Number: US 2014/0193974 A1
- Document ID: US20140193974A1
- Status: Published application
- Kind: A1
- Application number: 13/737,192
- Filed: 2013-01-09
- Published: 2014-07-10
- Earliest claimed: 2013-01-09
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chia-Ying LEE; Jyu-Horng SHIEH
- Web page: https://patentgrep.com/patent/US20140193974A1

## CPC

- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10P 50/283: {by chemical means}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/405: {characterised by their composition, e.g. multilayer masks}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- Y10S 438/947: Subphotolithographic processing
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A multi-patterning method includes: patterning at least two first openings in a hard mask layer over a substrate using a first mask; forming spacers within two of the at least two first openings, each spacer having a spacer opening therein for patterning a respective first circuit pattern over the substrate, wherein each spacer defines a pattern-free region adjacent to a respective one of the at least two first circuit patterns, and patterning a second circuit pattern in the hard mask layer using a second mask. The second circuit pattern is located between and excluded from the pattern free regions adjacent the at least two first circuit patterns.

## Claims

### Claim 1

A multi-patterning method comprising:
patterning at least two first openings in a hard mask layer over a substrate using a first mask;
forming spacers within two of the at least two first openings, each spacer having a spacer opening therein for patterning a respective first circuit pattern over the substrate, wherein each spacer defines a pattern-free region adjacent to a respective one of the at least two first circuit patterns, and
patterning a second circuit pattern in the hard mask layer using a second mask, wherein the second circuit pattern is located between and excluded from the pattern-free regions adjacent the at least two first circuit patterns.

### Claim 2 (depends on 1)

The method of claim 1, wherein a distance between the at least two first openings in the hard mask layer is a line width of the second circuit pattern.

### Claim 3 (depends on 1)

The method of claim 1, wherein a distance between the second circuit pattern and one of the at least two first circuit patterns is less than a minimum spacing between two lines to be clearly patterned using a single mask.

### Claim 4 (depends on 1)

The method of claim 1, wherein the spacer forming step includes:
forming a conformal layer of a spacer material over the substrate and the hard mask layer; and
etching the conformal layer to remove portions of the conformal layer above a height of a top surface of the hard mask layer.

### Claim 5 (depends on 4)

The method of claim 4, wherein the etching step is an anisotropic etch, and the etching step forms the spacer openings.

### Claim 6 (depends on 5)

The method of claim 5, wherein the anisotropic etch is a reactive ion etch.

### Claim 7 (depends on 4)

The method of claim 4, wherein:
the hard mask layer comprises one of the group consisting of SiO, SiON, and SiN; and
the spacer material is a metal.

### Claim 8 (depends on 7)

The method of claim 7, wherein the metal comprises one of the group consisting of Ti, Ta, TaN, TiO, TiN, and TaN.

### Claim 9 (depends on 4)

The method of claim 4, wherein the step of patterning the second circuit pattern includes selectively etching portions of the hard mask without substantially etching the spacer material.

### Claim 10

A multi-patterning method comprising:
patterning at least two first openings in a hard mask layer over a substrate using a first mask;
forming a conformal layer of a spacer material over the substrate and the hard mask layer; and
anisotropically etching the conformal layer to remove portions of the conformal layer above a height of a top surface of the hard mask layer to form spacers within each of the at least two first openings, each spacer having a spacer opening therein for forming a respective first circuit pattern over the substrate, wherein each spacer comprises the spacer material defining a pattern-free region adjacent to a respective one of the at least two first circuit patterns, and
selectively etching portions of the hard mask without substantially etching the spacer material, for forming a second circuit pattern trench in the hard mask layer using a second mask, wherein the second circuit pattern trench is located between and excluded from the pattern-free regions adjacent the at least two first circuit patterns.

### Claim 11 (depends on 10)

The method of claim 10, wherein:
the hard mask layer is a top hard mask layer, and the substrate comprises a bottom hard mask layer between the substrate and the top hard mask layer, and a center hard mask layer between the bottom and top hard mask layers; and
the step of selectively etching etches through the portions of the top hard mask without etching through the center hard mask.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
anisotropically etching through exposed portions of the center hard mask without etching through the bottom hard mask or the remaining spacer material or remaining portions of the top hard mask; and
anisotropically etching to remove exposed portions of the bottom hard mask, and the remaining spacer material and portions of the top hard mask.

### Claim 13 (depends on 11)

The method of claim 11, further comprising filling the spacer openings and second circuit pattern trench with a conductive material, to form the first and second circuit patterns.

### Claim 14 (depends on 10)

The method of claim 10, wherein the spacers have a width which defines a minimum spacing between a pattern formed using the first mask and a pattern formed using the second mask, regardless of an overlay error between a positions of the second mask and the pattern formed by the first mask during a photo exposure of the substrate using the second mask.

### Claim 15 (depends on 10)

The method of claim 10, wherein:
the patterning step includes forming at least three first openings;
the anisotropically etching step forms at least three spacers;
the selectively etching step forms at least two second circuit pattern trenches;
the second mask has an overlay error with respect to the locations of the first openings;
a first one of the second circuit patterns is located with a position error relative to an adjacent first pattern due to the overlay error; and
a second one of the second circuit patterns is located without a position error relative to the adjacent first pattern, regardless of the overlay error.

### Claim 16 (depends on 10)

The method of claim 10, wherein the conformal layer has a thickness which is approximately the thickness of the hard mask layer.

### Claim 17

A method, comprising:
forming a plurality of spacers in a hard mask layer above a semiconductor substrate, each spacer having a perimeter defined using a first photomask, and an interior opening defining a first circuit pattern; and
patterning the hard mask layer using a second photomask for forming at least one second circuit pattern between two of the plurality of spacers, wherein the spacers have a width defining a minimum distance between the second circuit pattern and any of the first circuit patterns.

### Claim 18 (depends on 17)

The method of claim 17, wherein the spacer forming step includes:
forming a conformal layer of a spacer material over the substrate and hard mask layer; and
etching the conformal layer, to remove portions of the conformal layer above a height of a top surface of the hard mask layer.

### Claim 19 (depends on 17)

The method of claim 17, wherein the first circuit patterns and second circuit patterns have locations defined by a design layout, wherein at least one of the second circuit patterns is separated from an adjacent one of the first circuit patterns by a distance that does not deviate from the design layout, regardless of an overlay error between the second photomask and the first circuit pattern.

### Claim 20 (depends on 19)

The method of claim 19, wherein at least another one of the second circuit patterns is separated from an adjacent one of the first circuit patterns by a distance that deviates from the design layout because of the overlay error.