# US 2014/0193973 A1 · Method for forming interlayer connectors to a stack of conductive layers

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- Number: US 2014/0193973 A1
- Document ID: US20140193973A1
- Status: Published application
- Kind: A1
- Application number: 13/735,922
- Filed: 2013-01-07
- Published: 2014-07-10
- Earliest claimed: 2013-01-07
- Assignees: Macronix International Co., Ltd.
- Inventors: Shih-Hung CHEN
- Web page: https://patentgrep.com/patent/US20140193973A1

## CPC

- H10W 20/031: {of conductive parts of the interconnections}
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 76/204: {of organic photoresist masks}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method forms interlayer connectors extending to conductive layers of a stack of W conductive layers interleaved with dielectric layers. The stack is etched to expose landing areas at W−1 conductive layers using a set of M etch masks. For each etch mask m, m going from 0 to M−1, there is a first etching step, at least one mask trimming step, and a subsequent etching step following each trimming step. The etch mask may cover Nm+1 of the landing areas and the open etch region may cover Nm of the landing areas. N equals 2 plus the number of trimming steps. The trimming step may be carried out so that the increased size open etch region overlies an additional 1/N of the landing areas. Part of the stack surface may be shielded during the removing step to create dummy areas without contact openings.

## Claims

### Claim 1

A method, for use with an electronic device including a stack comprising a plurality of conductive layers interleaved with a plurality of dielectric layers, for forming interlayer connectors extending to respective ones of the plurality of conductive layers, the method comprising:
removing portions of the conductive layers and the dielectric layers in the stack to form landing areas on the plurality of conductive layers in the stack, the landing areas without overlying conductive layers in the stack, wherein W is the number of conductive layers, the removing step comprising:
etching the stack of dielectric/conductive layers to expose landing areas at W−1 conductive layers using a set of M etch masks, the etch masks having mask regions and spaced apart open etch regions, with M being greater than or equal to 2, and with NM being less than or equal to W, where N is an integer greater than or equal to 3;
for each etch mask m in the set, where m goes from 0 to M−1:
(a) form etch mask m over the contact region, the etch mask having open etch regions over some of the landing areas;
(b) etch through Nm conductive layers at the open etch regions of mask m; (c) trim etch mask m to increase the size of the open etch regions to overlie additional contact openings;
(d) etch Nm conductive layers at the increased size open etch regions; and
(g) if N is greater than 3, repeat the (c) trim step and the (d) etch step N−3 times.
whereby the landing areas on the plurality of conductive layers are exposed with different combinations of the etch masks.

### Claim 2 (depends on 1)

The method according to claim 1, further comprising:
applying a dielectric fill over the landing areas;
creating contact openings down to the landing areas through the dielectric fill; and
filling the openings with a conductive material thereby forming interlayer connectors.

### Claim 3 (depends on 1)

The method according to claim 1, further comprising selecting N as equal to 2 plus the number of trim steps for each etch mask.

### Claim 4 (depends on 1)

The method according to claim 1, wherein etch mask 0 has a 0 mask width with an open etch region having an open region width equal to about the 0 mask width divided by N.

### Claim 5 (depends on 1)

The method according to claim 1, wherein each etch mask has a mask width with an open etch region having an open region width equal to about the mask width divided by N.

### Claim 6 (depends on 1)

The method according to claim 1, wherein in the (a) etch mask forming step, the etch mask covers Nm+1 landing areas and the open etch region covers Nm of the landing areas.

### Claim 7 (depends on 1)

The method according to claim 1, wherein in the (a) etch mask forming step, the open etch regions are over about Nm of the landing areas.

### Claim 8 (depends on 1)

The method according to claim 1, wherein W=27 and N=3 so that:
for m=1:
the (b) etch step is carried out to etch 1 conductive layer; and
the (d) etch step is carried out to etch 1 conductive layer;
for m=2:
the (b) etch step is carried out to etch 3 conductive layers; and
the (d) etch step is carried out to etch 3 conductive layers; and
for m=3:
the (b) etch step is carried out to etch 9 conductive layers; and
the (d) etch step is carried out to etch 9 conductive layers.

### Claim 9 (depends on 1)

The method according to claim 1, wherein the trimming step is carried out so that the increased size open etch regions overlie about an additional 1/N of the landing areas.

### Claim 10 (depends on 1)

The method according to claim 1, wherein the device includes a surface over the stack, and further comprising shielding a portion of the surface during the removing step to create dummy areas without contact openings.

### Claim 11

A method, for use with an integrated circuit device including a stack comprising a plurality of conductive layers interleaved with a plurality of dielectric layers, for forming interlayer connectors extending to respective ones of the plurality of conductive layers, the method comprising:
removing portions of the conductive layers and the dielectric layers in the stack to form landing areas on the plurality of conductive layers in the stack, the landing areas without overlying conductive layers in the stack, wherein said removing includes using a set of M etch masks with M being greater than or equal to 2, and with NM being less than or equal to W, the etch masks having mask regions and spaced apart open etch regions corresponding to selected landing areas, wherein W is the number of total conductive layers; for each etch mask m, where m goes from 0 to M−1, etching Nm conductive layers over up to 1/N of the landing areas, trimming the etch mask m, and etching Nm conductive layers over up to 1/N of the landing areas, so that the landing areas on the plurality of conductive layers are exposed with different combinations of the etch masks.

### Claim 12 (depends on 11)

The method according to claim 11, wherein when N=3, each etch mask is trimmed once between etching the conductive layers.

### Claim 13 (depends on 11)

The method according to claim 11, wherein when N=4, each etch mask is trimmed twice between etching conductive layers.

### Claim 14 (depends on 11)

The method according to claim 11, wherein the spaced apart open etch regions overlie about 1/N of the contact openings.

### Claim 15 (depends on 14)

The method according to claim 14, wherein trimming is carried out to create an increased size open etch region overlying about an additional 1/N of the contact openings.

### Claim 16 (depends on 11)

The method according to claim 11, further comprising forming interlayer connectors extending to the landing areas of the conductive layers.

### Claim 17 (depends on 16)

The method according to claim 16, wherein the interlayer connectors forming step comprises:
filling over the landing areas with a dielectric fill material; and
using a patterned etching process and a conductive material deposition process to form the interlayer connectors extending through the dielectric fill material to the landing areas in the plurality of conductive layers.

### Claim 18 (depends on 11)

The method according to claim 11, wherein the device includes a surface over the stack, and further comprising shielding a portion of the surface during the portions removing step.

### Claim 19 (depends on 18)

The method according to claim 18, wherein the shielding step is carried out using a hard mask layer at the surface.

### Claim 20

A set of etch masks for use in exposing landing areas on a plurality of conductive layers interleaved with a plurality of dielectric layers comprising:
a set of M etch masks, the etch masks having mask regions and spaced apart open etch regions, where M is an integer greater than or equal to 2 and N is an integer greater than or equal to 3;
for each etch mask m in the set, where m goes from 0 to M−1, the etch mask covers landing areas on Nm+1 of the conductive layers and the open etch region covers landing areas on Nm of the conductive layers.