# US 2014/0193972 A1 · Buried Hard Mask for Embedded Semiconductor Device Patterning

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- Number: US 2014/0193972 A1
- Document ID: US20140193972A1
- Status: Published application
- Kind: A1
- Application number: 13/735,156
- Filed: 2013-01-07
- Published: 2014-07-10
- Earliest claimed: 2013-01-07
- Assignees: Spansion LLC
- Applicants: Spansion LLC
- Inventors: Scott A. BELL; Angela Tai HUI; Simon S. CHAN
- Web page: https://patentgrep.com/patent/US20140193972A1

## CPC

- H10B 41/30: characterised by the memory core region
- H10B 41/49: comprising different types of peripheral transistor
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 70/658: {for devices provided for in groups H10D8/00 - H10D48/00}
- H10W 70/662: {Semiconductor materials}
- H10W 70/69: Insulating materials thereof
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Methods and apparatus for manufacturing semiconductor devices, and such semiconductor devices, are described. According to various aspects of the disclosure, a semiconductor device can be manufactured by forming a core region of the semiconductor device and forming a periphery region of the semiconductor device. A first polysilicon region can then be formed over the core and periphery regions of the semiconductor device. A first mask is formed on the first poly silicon layer and a second polysilicon layer is disposed such that the second polysilicon layer covers the first mask. A second mask can then be formed on the second polysilicon layer. After forming the second mask, portions of the first and second polysilicon layers that are uncovered by either the first or second masks are removed.

## Claims

### Claim 1

A method of manufacturing an embedded semiconductor device, comprising:
forming a core region of the semiconductor device;
forming a periphery region of the semiconductor device;
disposing a first polysilicon layer over the core and periphery regions of the semiconductor device;
forming a first mask on the first polysilicon layer;
disposing a second polysilicon layer such that the second polysilicon layer covers the first mask;
forming a second mask on the second polysilicon layer; and
removing portions of the first and second polysilicon layers that are uncovered by either of the first and second masks.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first mask is disposed on the periphery region of the semiconductor device.

### Claim 3 (depends on 2)

The method of claim 2, further comprising forming logic gates from a portion of the periphery region that is masked by the first mask.

### Claim 4 (depends on 1)

The method of claim 1, wherein the second mask is disposed on the core portion of the semiconductor device.

### Claim 5 (depends on 4)

The method of claim 4, further comprising forming bitlines or writelines from a portion of the core region that is masked by the second mask.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first and second masks comprise oxides, nitrides, or an oxide/nitride combination.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first and second masks comprise the same material.

### Claim 8 (depends on 1)

The method of claim 1, further comprising forming one or more memory elements in the core region of the semiconductor.

### Claim 9 (depends on 1)

The method of claim 1, further comprising forming one or more logical devices in the periphery region of the semiconductor.

### Claim 10 (depends on 1)

The method of claim 1, wherein the removed portions of the first and second polysilicon layers are removed from the core and periphery regions simultaneously.

### Claim 11

An apparatus, comprising:
a semiconductor fabrication module; and
a controller configured to cause the semiconducting fabrication module to:
form a core region of a semiconductor device;
form a periphery region of the semiconductor device;
dispose a first polysilicon layer over the core and periphery regions of the semiconductor device;
form a first mask on the first polysilicon layer;
dispose a second polysilicon layer such that the second polysilicon layer covers the first mask;
form a second mask on the second polysilicon layer; and
remove portions of the first and second polysilicon layers that are uncovered by either of the first and second masks.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the controller is further configured to cause the fabrication module to dispose the first mask on the periphery region of the semiconductor device.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein the controller is further configured to cause the fabrication module to form logic gates from a portion of the periphery region that is masked by the first mask.

### Claim 14 (depends on 11)

The apparatus of claim 11, wherein the controller is further configured to cause the fabrication module to dispose the second mask on the core portion of the semiconductor device.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the controller is further configured to cause the fabrication module to form bitlines or writelines from a portion of the core region that is masked by the second mask.

### Claim 16 (depends on 11)

The apparatus of claim 11, wherein the first and second masks comprise oxides, nitrides, or an oxide/nitride combination.

### Claim 17 (depends on 11)

The apparatus of claim 11, wherein the first and second masks comprise the same material.

### Claim 18 (depends on 11)

The apparatus of claim 11, wherein the controller is further configured to cause the fabrication module to form one or more memory elements in the core region of the semiconductor.

### Claim 19 (depends on 1)

The apparatus of claim 1, wherein the controller is further configured to cause the fabrication module to form one or more logical devices in the periphery region of the semiconductor.

### Claim 20 (depends on 1)

The apparatus of claim 1, wherein the controller is further configured to cause the fabrication module to remove the removed portions of the first and second polysilicon layers from the core and periphery regions simultaneously.