# US 2014/0193968 A1 · Semiconductor Device and Manufacturing Method of the Same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0193968 A1 - Document ID: US20140193968A1 - Status: Published application - Kind: A1 - Application number: 14/100,462 - Filed: 2013-12-09 - Published: 2014-07-10 - Earliest claimed: 2005-05-20 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Yoshito Nakazawa; Yuji Yatsuda - Web page: https://patentgrep.com/patent/US20140193968A1 ## CPC - H10D 84/148: {the built-in components being breakdown diodes, e.g. Zener diodes} - H10D 30/023: {having multiple independently-addressable gate electrodes influencing the same channel (manufacture or treatment of dual gate TFTs H10D30/031)} - H10D 30/0295: {using recessing of the source electrodes} - H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes} - H10D 30/665: {having edge termination structures} - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 64/013: {of electrodes having a conductor capacitively coupled to a semiconductor by an insulator} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates} - H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates} - H10D 64/516: {the thicknesses being non-uniform} - H10D 64/519: {characterised by their top-view geometrical layouts} - H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)} - H10D 89/611: {using diodes as protective elements} - H10P 14/43: Chemical deposition, e.g. chemical vapour deposition [CVD] - H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge - H10D 64/62: Electrodes ohmically coupled to a semiconductor - H10W 72/926: {Multiple bond pads having different sizes} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method for manufacturing a semiconductor device having a field-effect transistor, including forming a trench in a semiconductor substrate, forming a first insulating film in the trench, forming an intrinsic polycrystalline silicon film over the first insulating film, and introducing first conductive type impurities into the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. Next, a second insulating film is formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film, upper part of the trench ton form a second gate electrode. ## Claims ### Claim 1 A method for manufacturing a semiconductor device including a field-effect transistor, comprising steps of: (a) forming a trench in a semiconductor substrate; (b) forming a first insulating film in the trench; (c) forming an intrinsic polycrystalline silicon film over the first insulating film; (d) introducing impurities of a first conductivity type into the intrinsic polycrystalline silicon film to form a first conductive film; (e) after the step (d), etching the first conductive film so as to provide a portion of the first conductive film in a lower part of the trench, thereby to form a first gate electrode of the field-effect transistor; (f) forming a second insulating film in the trench, wherein the second insulating film is disposed above the first insulating film and the first gate electrode; (g) forming a doped polycrystalline silicon film of the first conductivity type, having higher impurity concentration than the first gate electrode, over the second insulating film; and (h) etching the doped polycrystalline silicon film so as to provide a portion of the doped polycrystalline silicon film in an upper part of the trench, thereby to form a second gate electrode of the field-effect transistor. ### Claim 2 (depends on 1) A method for manufacturing a semiconductor device according to the claim 1, wherein, at the step (e), a first lead-out part of the first gate electrode is formed in an outer peripheral portion of the trench and is electrically connected to the first gate electrode, and wherein, at the step (h), a second lead-out part of the second gate electrode is formed in the outer peripheral portion of the trench and is electrically connected to the second gate electrode. ### Claim 3 (depends on 2) A method for manufacturing a semiconductor device according to the claim 2, wherein a thickness of the first lead-out part is smaller than a thickness of the second lead-out part. ### Claim 4 (depends on 1) A method for manufacturing a semiconductor device according to the claim 1, wherein a thickness of the first insulating film is larger than a thickness of the second insulating film. ### Claim 5 (depends on 1) A method for manufacturing a semiconductor device according to the claim 1, further comprising forming the first insulating film by a thermal oxidation process. ### Claim 6 (depends on 1) A method for manufacturing a semiconductor device according to the claim 1, further comprising forming the second insulating film by a thermal oxidation process. ### Claim 7 (depends on 1) A method for manufacturing a semiconductor device according to the claim 1, further comprising, at the step (g), forming the doped polycrystalline silicon film by a CVD method. ### Claim 8 (depends on 1) A method for manufacturing a semiconductor device according to the claim 1, wherein the first conductivity type is n-type conductivity. ### Claim 9 A method for manufacturing a semiconductor device including a field-effect transistor, comprising steps of: (a) forming a trench in a semiconductor substrate; (b) forming a first gate electrode of the field-effect transistor in the trench; and (c) forming a second gate electrode of the field-effect transistor in the trench and over the first gate electrode, wherein the step (b) includes steps of forming an intrinsic polycrystalline silicon film in the trench and introducing impurities into the intrinsic polycrystalline silicon film, wherein the step (c) includes a step of forming a doped polycrystalline silicon film in the trench by a CVD method, and wherein an impurity concentration of the first gate electrode is lower than an impurity concentration of the second gate electrode. ### Claim 10 (depends on 9) A method for manufacturing a semiconductor device according to the claim 9, wherein a first lead-out part of the first gate electrode is formed in an outer peripheral portion of the trench and is electrically connected to the first gate electrode, and wherein a second lead-out part of the second gate electrode is formed in the outer peripheral portion of the trench and is electrically connected to the second gate electrode. ### Claim 11 (depends on 10) A method for manufacturing a semiconductor device according to the claim 10, wherein a thickness of the first lead-out part is smaller than a thickness of the second lead-out part. ### Claim 12 (depends on 9) A method for manufacturing a semiconductor device according to the claim 9, wherein a thickness of the first insulating film is larger than a thickness of the second insulating film. ### Claim 13 (depends on 9) A method for manufacturing a semiconductor device according to the claim 9, further comprising forming the first insulating film is formed by a thermal oxidation process. ### Claim 14 (depends on 9) A method for manufacturing a semiconductor device according to the claim 9, wherein the second insulating film is formed by a thermal oxidation process. ### Claim 15 (depends on 9) A method for manufacturing a semiconductor device according to the claim 9, wherein the first and second gate electrode are an n-type, respectively.