# US 2014/0193962 A1 · Semiconductor devices and methods of forming the same

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- Number: US 2014/0193962 A1
- Document ID: US20140193962A1
- Status: Published application
- Kind: A1
- Application number: 14/202,629
- Filed: 2014-03-10
- Published: 2014-07-10
- Earliest claimed: 2012-12-06
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: YONGDON KIM
- Web page: https://patentgrep.com/patent/US20140193962A1

## CPC

- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/64: Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/159: {Shapes}
- H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 46/301: {for alignment}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of forming a semiconductor device is provided. The method includes preparing a substrate having a transistor region and an alignment region, forming a first trench and a second trench in the substrate of the transistor region and in the substrate of the alignment region, respectively, forming a drift region in the substrate of the transistor region, forming two third trenches respectively adjacent to two ends of the drift region, and forming an isolation pattern in the first trench, a buried dielectric pattern in the second trench, and dielectric patterns in the two third trenches, respectively. A depth of the first trench is less than a depth of the third trenches, and the depth of the first trench is equal or substantially equal to a depth of the second trench.

## Claims

### Claim 1

A method of forming a semiconductor device, the method comprising:
preparing a substrate having a transistor region and an alignment region;
forming a first trench and a second trench in the substrate of the transistor region and in the substrate of the alignment region, respectively;
forming a drift region in the substrate of the transistor region;
forming two third trenches respectively adjacent to two ends of the drift region; and
forming an isolation pattern in the first trench, a buried dielectric pattern in the second trench, and dielectric patterns in the two third trenches, respectively,
wherein a depth of the first trench is less than a depth of the third trenches, and the depth of the first trench is equal or substantially equal to a depth of the second trench.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first and second trenches are simultaneously formed using a single patterning process.

### Claim 3 (depends on 1)

The method of claim 1, wherein the second trench is used as an alignment key in subsequent exposure processes.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming the drift region includes implanting dopants of a first conductivity type into the substrate surrounding the first trench in the transistor region.

### Claim 5 (depends on 4)

The method of claim 4, further comprising forming a first well region and a second well region in the drift region,
wherein the first well region is formed between one of the dielectric patterns and the isolation pattern,
wherein the first well region is formed to be spaced apart from the isolation pattern, and
wherein the second well region is formed between the other of the dielectric patterns and the isolation pattern.

### Claim 6 (depends on 5)

The method of claim 5, wherein the first well region is formed by implanting dopants of a second conductivity type different from the first conductivity type, and the second well region is formed by implanting dopants of the first conductivity type.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the isolation pattern, the buried dielectric pattern and the dielectric patterns includes:
forming a dielectric layer in the first, second and third trenches and on the substrate; and
planarizing the dielectric layer until a top surface of the substrate is exposed.

### Claim 8 (depends on 1)

The method of claim 1, wherein a bottom surface of the first trench is flat such that a depth of the first trench is uniform throughout the entire bottom surface of the first trench.