# US 2014/0193957 A1 · Reducing gate height variance during semiconductor device formation

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- Number: US 2014/0193957 A1
- Document ID: US20140193957A1
- Status: Published application
- Kind: A1
- Application number: 13/738,270
- Filed: 2013-01-10
- Published: 2014-07-10
- Earliest claimed: 2013-01-10
- Assignees: Globalfoundries Inc.
- Applicants: Globalfoundries Inc.
- Inventors: Ashish K. Jha; Tae-Hoon Kim; Tae Hoon Lee; Chang Ho Maeng; Songkram Srivathanakul; Haiting Wang
- Web page: https://patentgrep.com/patent/US20140193957A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0179: {the gate conductors having different shapes or dimensions}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/8316: {the IGFETs characterised by having gate sidewall spacers specially adapted for integration}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates. A liner layer and an inter-layer dielectric are formed over the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates, and the set of dummy gates are then removed. The result is a set of gate regions having less height variance/disparity.

## Claims

### Claim 1

A method for reducing gate height variance in a semiconductor device, comprising:
removing a hard mask layer and a set of spacers from a set of dummy gates;
depositing a liner layer and an inter-layer dielectric (ILD) over the set of dummy gates;
removing the liner layer from at least a portion of a top surface of the set of dummy gates; and
removing the set of dummy gates.

### Claim 2 (depends on 1)

The method of claim 1, the semiconductor device comprising a transistor.

### Claim 3 (depends on 2)

The method of claim 2, the transistor comprising:
a substrate;
a NFET region formed over the substrate; and
a PFET region formed over the substrate.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
a set of reversely switched dinistors (RSDS) in the NFET region; and
a set of silicon germanium (SiGe) regions in the PFET region.

### Claim 5 (depends on 1)

The method of claim 1, the set of dummy gates comprising poly silicon.

### Claim 6 (depends on 1)

The method of claim 1, the liner layer comprising nitride.

### Claim 7 (depends on 1)

The method of claim 1, further comprising polishing the ILD.

### Claim 8 (depends on 1)

The method of claim 1, the liner layer being removed via polishing or etching.

### Claim 9 (depends on 1)

The method of claim 1, further comprising a semiconductor device formed according to the method of claim 1.

### Claim 10

A method for reducing gate height variance in a semiconductor device, comprising:
removing a hard mask layer and a set of spacers from a first gate stack and a second gate stack, the first gate stack having a first dummy gate, and the second gate stack having a second dummy gate;
depositing a liner layer and an inter-layer dielectric (ILD) over the first dummy gate and the second dummy gate;
removing the liner layer from at least a portion of a top surface of the first dummy gate and the second dummy gate; and
removing the set of dummy gates to reduce a height variance between the first gate stack and the second gate stack.

### Claim 11 (depends on 10)

The method of claim 10, the semiconductor device comprising a transistor.

### Claim 12 (depends on 11)

The method of claim 11, the transistor comprising:
a substrate;
a NFET region formed over the substrate; and
a PFET region formed over the substrate.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
a set of reversely switched dinistors (RSDS) in the NFET region; and
a set of silicon germanium (SiGe) regions in the PFET region.

### Claim 14 (depends on 10)

The method of claim 10, the set of dummy gates comprising poly silicon.

### Claim 15 (depends on 10)

The method of claim 10, the liner layer comprising nitride.

### Claim 16 (depends on 10)

The method of claim 10, further comprising polishing the ILD.

### Claim 17 (depends on 10)

The method of claim 10, the liner layer being removed via polishing or etching.

### Claim 18 (depends on 1, 10)

The method of claim 10, further comprising a semiconductor device formed according to the method of claim 1.

### Claim 19

A method for reducing gate height variance in a semiconductor device, comprising:
identifying a height variance between a first gate stack and a second gate stack of a semiconductor device, the first gate stack having a first dummy gate and the second gate stack having a second dummy gate;
removing a hard mask layer and a set of spacers from the first gate stack and the second gate stack;
depositing a liner layer and an inter-layer dielectric (ILD) over the first dummy gate and the second dummy gate;
removing the liner layer from at least a portion of a top surface of the first dummy gate and the second dummy gate; and
removing the set of dummy gates to reduce the height differential between the first gate stack and the second gate stack.

### Claim 20 (depends on 1, 19)

The method of claim 19, further comprising a semiconductor device formed according to the method of claim 1.