# US 2014/0193956 A1 · Transistor and fabriation method

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- Number: US 2014/0193956 A1
- Document ID: US20140193956A1
- Status: Published application
- Kind: A1
- Application number: 14/143,623
- Filed: 2013-12-30
- Published: 2014-07-10
- Earliest claimed: 2013-01-08
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation
- Inventors: DE YUAN XIAO
- Web page: https://patentgrep.com/patent/US20140193956A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/637: {Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/05: using Group III-V technology
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Fabrication methods for junctionless transistor and complementary junctionless transistor are provided. An isolation layer doped with a first-type ion is formed on a semiconductor substrate and an active layer doped with a second-type ion is formed on the isolation layer. The active layer includes a first portion between a second portion and a third portion of the active layer. Portions of the isolation layer under the second and third portions of the active layer are removed to suspend the second and third portions of the active layer. A gate structure is formed on the first portion of the active layer. A source and a drain are formed by doping the second portion and the third portion of the active layer with the second-type ion on both sides of the gate structure. The source and the drain have a same doping type as the first portion of the active layer.

## Claims

### Claim 1

A method for forming a junctionless transistor device comprising:
providing a semiconductor substrate, and forming a first-type doped well in the substrate;
forming an isolation layer doped with a first-type ion on the semiconductor substrate and an active layer doped with a second-type ion on the isolation layer, wherein the active layer includes a first portion between a second portion and a third portion of the active layer;
removing portions of the isolation layer under the second and third portions of the active layer to suspend the second and third portions of the active layer;
forming a dielectric layer between the semiconductor substrate and the active layer, wherein the dielectric layer has a same thickness of the isolation layer;
forming a gate structure on the first portion of the active layer; and
forming a source and a drain by doping the second portion and the third portion of the active layer with the second-type ion on both sides of the gate structure, wherein the source and the drain have a same doping type as the first portion of the active layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein removing the isolation layer under the second and the third portions of the active layer includes:
forming a photoresist layer on the active layer, wherein the photoresist layer covers the first portion of the active layer; and
using a selective etching process to etch the isolation layer from opposing ends of the isolation layer such that etched sidewalls of the isolation layer are aligned with or within corresponding sidewalls of the photoresist layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the selective etching process includes a chemical vapor etching process.

### Claim 4 (depends on 2)

The method of claim 2, wherein the selective etching process includes a temperature ranging from about 300° C. to about 800° C., and an etching gas including a mixture of H2 and HCl, wherein a partial pressure of HCl is about 300 Torr to about 500 Torr.

### Claim 5 (depends on 1)

The method of claim 1, wherein the active layer and the isolation layer are made of materials having an etching selectivity, and the semiconductor substrate and the isolation layer are made of materials having an etching selectivity.

### Claim 6 (depends on 1)

The method of claim 1, wherein the isolation layer is made of SiGe or GaAs.

### Claim 7 (depends on 1)

The method of claim 1, wherein the active layer is made of Si or Ge.

### Claim 8 (depends on 1)

The method of claim 1, wherein the active layer is made of a group III-V compound.

### Claim 9 (depends on 1)

The method of claim 1, wherein each of the source and the drain has a doping concentration greater than 2E19 atoms/cm2.

### Claim 10 (depends on 1)

The method of claim 1, wherein the dielectric layer is made of a material including silicon oxide, silicon nitride oxide, boron-doped glass, phosphorus-doped glass, and/or boron-and phosphorus-doped glass.

### Claim 11

A method for forming a complementary junctionless transistor device comprising:
providing a semiconductor substrate, wherein the semiconductor substrate includes an NFET (N-field-effect transistor) portion and a PFET portion neighboring with each other;
forming an isolation layer on the semiconductor substrate and an active layer on the isolation layer;
forming a P-well in the NFET portion of the semiconductor substrate, and forming an N-well in the PFET portion of the semiconductor substrate;
forming a P-doped isolation layer by doping a portion of the isolation layer on the NFET portion, and forming an N-doped isolation layer by doping a portion of the isolation layer on the NFET portion;
forming an N-doped active layer by doping a portion of the active layer on the P-doped isolation layer, and forming a P-doped active layer by doping a portion of the active layer on the N-doped isolation layer;
etching the active layer and the isolation layer to form an opening to expose a surface of the semiconductor substrate covering an interface portion between the NFET portion and PFET portion;
removing a portion of the P-doped isolation layer to suspend the N-doped active layer from opposing ends of the N-doped active layer, and removing a portion of the N-doped isolation layer to suspend the P-doped active layer from opposing ends of the P-doped active layer;
forming a dielectric layer between the N-doped active layer and the semiconductor substrate, between the P-doped active layer and the semiconductor substrate, and in the opening;
forming a first gate structure on the N-doped active layer disposed on a remaining P-doped isolation layer, forming a second gate structure on the P-doped active layer disposed on a remaining N-doped isolation layer; and
forming an N-doped source and an N-doped drain in the N-doped active layer on both sides of the first gate structure, and forming a P-doped source and a P-doped drain in the P-doped active layer on both sides of the second gate structure.

### Claim 12 (depends on 11)

The method of claim 11, wherein removing the portion of the P-doped isolation layer to suspend the N-doped active layer, and removing the portion of the N-doped isolation layer to suspend the P-doped active layer includes:
forming a photoresist layer on the N-doped active layer and P-doped active layer, wherein the photoresist layer covers the interface portion between the N-doped active layer and P-doped active layer; and
using a selective etching process to etch inward from the opposing ends of each of the P-doped isolation layer and the N-doped isolation layer such that etched sidewalls of each of the P-doped isolation layer and N-doped isolation layer are aligned with corresponding sidewalls of the photoresist layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein the selective etching process includes a chemical vapor etching process.

### Claim 14 (depends on 12)

The method of claim 12, wherein the selective etching process includes a temperature ranging from about 300° C. to about 800° C., and an etching gas including a mixture of H2 and HCl, wherein a partial pressure of HCl is about 300 Torr to about 500 Torr.

### Claim 15 (depends on 11)

The method of claim 11, wherein the active layer and the isolation layer are made of materials having an etching selectivity, and the semiconductor substrate and the isolation layer are made of materials having an etching selectivity.

### Claim 16 (depends on 11)

The method of claim 11, wherein the isolation layer is made of SiGe or GaAs.

### Claim 17 (depends on 11)

The method of claim 11, wherein the active layer is made of Si or Ge.

### Claim 18 (depends on 11)

The method of claim 11, wherein the active layer is made of a group III-V compound.

### Claim 19 (depends on 11)

The method of claim 11, wherein each of the source and the drain has a doping concentration greater than 2E19 atoms/cm2.

### Claim 20 (depends on 11)

The method of claim 11, wherein the dielectric layer is made of a material including silicon oxide, silicon nitride oxide, boron-doped glass, phosphorus-doped glass, and/or boron-and phosphorus-doped glass.