# US 2014/0193955 A1 · Hybrid Fin Field-Effect Transistor Structures and Related Methods

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- Number: US 2014/0193955 A1
- Document ID: US20140193955A1
- Status: Published application
- Kind: A1
- Application number: 14/204,776
- Filed: 2014-03-11
- Published: 2014-07-10
- Earliest claimed: 2004-12-01
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Matthew T. Currie
- Web page: https://patentgrep.com/patent/US20140193955A1

## CPC

- H10D 30/798: {being provided in or under the channel regions}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6748: {having a multilayer structure or superlattice structure}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide.

## Claims

### Claim 1

A method for forming a structure, the method comprising:
providing a substrate having an insulator layer disposed thereon, and a first semiconductor layer disposed in contact with the insulator layer; and
forming a fin field-effect transistor on the substrate by:
patterning the first semiconductor layer to define a source region, a drain region, and at least one fin disposed between the source and the drain regions,
forming a second semiconductor layer along a sidewall of the fin, the second semiconductor layer being a same material as the first semiconductor layer,
forming a gate dielectric layer at least a portion of which is disposed over the fin, and
forming a gate over the gate dielectric layer disposed over the fin.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first semiconductor layer comprises a strained semiconductor layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the strained semiconductor layer is tensilely strained.

### Claim 4 (depends on 2)

The method of claim 2, wherein the strained semiconductor layer is compressively strained.

### Claim 5 (depends on 1)

The method of claim 1, wherein the second semiconductor layer is strained.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first semiconductor layer and the second semiconductor layer comprise a same type of strain.

### Claim 7 (depends on 1)

The method of claim 1, wherein the forming the second semiconductor layer along the sidewall of the fin includes conformally forming the second semiconductor layer along the sidewall and on a top of the fin, and removing a portion of the second semiconductor layer from the top of the fin.

### Claim 8 (depends on 1)

The method of claim 1 further comprising forming a salicide over the source region, drain region, and the gate.

### Claim 9 (depends on 1)

The method of claim 1, wherein the insulator is a crystalline material.

### Claim 10 (depends on 1)

The method of claim 1, wherein the fin comprises a portion of the insulator.

### Claim 11

A method comprising:
providing a substrate comprising a first semiconductor material;
patterning the first semiconductor material to form a fin;
forming a semiconductor layer of a second semiconductor material along a sidewall of the fin;
forming a gate dielectric layer at least a portion of which is disposed over the fin; and
forming a gate over the gate dielectric layer disposed over the fin.

### Claim 12 (depends on 11)

The method of claim 11, wherein the first semiconductor material is in a layer over an insulator.

### Claim 13 (depends on 12)

The method of claim 12, wherein the insulator is a crystalline material.

### Claim 14 (depends on 11)

The method of claim 11, wherein the first semiconductor material and the second semiconductor material are a same material.

### Claim 15 (depends on 11)

The method of claim 11, wherein the first semiconductor material is strained.

### Claim 16 (depends on 11)

The method of claim 11, wherein the second semiconductor material is strained.

### Claim 17 (depends on 11)

The method of claim 11, wherein the first semiconductor material and the second semiconductor material comprise a same type of strain.

### Claim 18 (depends on 11)

The method of claim 11, wherein the forming the semiconductor layer along the sidewall of the fin includes conformally forming the semiconductor layer along the sidewall and on a top of the fin, and removing a portion of the semiconductor layer from the top of the fin.

### Claim 19 (depends on 18)

The method of claim 18, wherein the semiconductor layer is formed over a mask on the top of the fin, wherein the removing the portion of the semiconductor layer from the top of the fin further includes removing the mask.

### Claim 20 (depends on 11)

The method of claim 11, wherein the substrate comprises an insulator, the first semiconductor material being over the insulator, fin comprising a portion of the insulator.