# US 2014/0193954 A1 · Method of manufacturing semiconductor device

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- Number: US 2014/0193954 A1
- Document ID: US20140193954A1
- Status: Published application
- Kind: A1
- Application number: 14/204,988
- Filed: 2014-03-11
- Published: 2014-07-10
- Earliest claimed: 2009-05-29
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Naoto Taoka; Atsushi Nakamura; Naozumi Morino; Toshikazu Ishikawa; Nobuhiro Kinoshita
- Web page: https://patentgrep.com/patent/US20140193954A1

## CPC

- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/427: {Power or ground buses}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10W 70/656: Fan-in layouts
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07554: {changes in dispositions}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/267: {Multiple bump connectors having different functions}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/547: {Dispositions of multiple bond wires}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9232: {with additional elements interposed between layers}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/951: {Materials of bond pads}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W 72/983: {Reinforcing structures, e.g. collars}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).

## Claims

### Claim at position 1

1-17. (canceled)

### Claim 18

A method of manufacturing a semiconductor device, comprising the steps of:
(a) providing a wiring substrate including a first surface, a plurality of bonding leads formed on the first surface, a plurality of solders respectively formed on the bonding leads, a second surface opposite to the first surface, and a plurality of lands formed on the second surface; and
(b) after the step (a), arranging a semiconductor chip over the first surface of the wiring substrate such that a main surface of the semiconductor chip faces the first surface of the wiring substrate, and respectively contacting a plurality of protruding electrodes of the semiconductor chip with the solders, the semiconductor chip including the main surface, a plurality of pads formed over the main surface, the protruding electrodes respectively formed over the pads, and a back surface opposite to the main surface,
wherein in the step (b), the solders are heated,
wherein the main surface of the semiconductor chip has a first area in which a core circuit is formed, and a second area surrounding the first area in plan view,
wherein the pads are formed in the second area but are not formed in the first area, in plan view,
wherein the plurality of pads includes a plurality of first pads arranged along sides of the main surface, and a plurality of second pads arranged along sides of the main surface and located closer to the first area than the plurality of first pads,
wherein each said second pad is a dummy pad, and
wherein each said second pad is arranged next to a first unique pad of the plurality of first pads such that a first unique electric current flows through each said second pad.

### Claim 19 (depends on 18)

The method according to claim 18, wherein a plurality of second unique pads is arranged such that a second unique electric current different from the first unique electric current flows through the plurality of second unique pads,
wherein one or more of said second pads is arranged between each said second unique pad in plan view, and
wherein a distance between each of said second unique pads is larger than a distance between each of said first pads.

### Claim 20 (depends on 18)

The method according to claim 18, wherein each of the second pad and the first unique pad has an opposite side facing to each other, and
wherein a center of the opposite side of the second pad is aligned with a center of the opposite side of the first unique pad.

### Claim 21 (depends on 18)

The method according to claim 18, wherein in the step (b), the plurality of solders is melted by heating both the wiring substrate and the semiconductor chip.

### Claim 22 (depends on 18)

The method according to claim 18, wherein each of the protruding electrodes comprises gold.