# US 2014/0193952 A1 · Methods for Metal Bump Die Assembly

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- Number: US 2014/0193952 A1
- Document ID: US20140193952A1
- Status: Published application
- Kind: A1
- Application number: 13/734,644
- Filed: 2013-01-04
- Published: 2014-07-10
- Earliest claimed: 2013-01-04
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Hsiu-Jen Lin; Ai-Tee Ang; Yu-Jen Tseng; Yu-Peng Tsai; Ming-Da Cheng; Chung-Shi Liu
- Web page: https://patentgrep.com/patent/US20140193952A1

## CPC

- H10W 72/072: {of bump connectors}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/0198: {batch processes}
- H10W 72/0711: {Apparatus therefor}
- H10W 72/01215: {forming coatings}
- H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01233: {in liquid form, e.g. spin coating, spray coating or immersion coating}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01251: {Changing the shapes of bumps}
- H10W 72/01253: {by etching}
- H10W 72/01255: {by using masks}
- H10W 72/01265: {Thermally treating (reflowing H10W72/01257)}
- H10W 72/019: {of bond pads}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/07125: {Means for controlling the bonding environment, e.g. valves or vacuum pumps}
- H10W 72/07141: {Means for applying energy, e.g. ovens or lasers}
- H10W 72/07202: {using auxiliary members}
- H10W 72/07204: {using temporary auxiliary members, e.g. sacrificial coatings}
- H10W 72/07211: {Treating the bond pad before connecting, e.g. by applying flux or cleaning}
- H10W 72/07235: {Applying EM radiation, e.g. induction heating or using a laser}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/223: {characterised by the structure of the outermost layers, e.g. multilayered coatings}
- H10W 72/225: {Bumps having a filler embedded in a matrix}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/253: {not comprising solid metals or solid metalloids, e.g. polymers or ceramics}
- H10W 72/255: {of outermost layers of multilayered bumps, e.g. material of a coating}
- H10W 72/281: {Auxiliary members}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/90: Bond pads, in general
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods for assembling metal bump dies. In an embodiment, a method includes providing an integrated circuit die having a plurality of conductive terminals; depositing solder to form solder depositions on the conductive terminals; providing a substrate having a die attach region on a surface for receiving the integrated circuit die, the substrate having a plurality of conductive traces formed in the die attach region; aligning the integrated circuit die and the substrate and bringing the plurality of conductive terminals and the conductive traces into contact, so that the solder depositions physically contact the conductive traces; and selectively heating the integrated circuit die and the conductive terminals to a temperature sufficient to cause the solder depositions to melt and reflow, forming solder connections between the conductive traces on the substrate and the conductive terminals on the integrated circuit die. Various energy sources are disclosed for the selective heating.

## Claims

### Claim 1

A method, comprising:
receiving an integrated circuit die having a plurality of conductive terminals extending from a surface of the integrated circuit die, the plurality of conductive terminals disposed on bond pads and providing electrical connection to one or more devices within the integrated circuit die;
forming solder depositions on the conductive terminals;
providing a substrate having a die attach region on a surface of the substrate for receiving the integrated circuit die and a protected region outside the die attach region, the substrate having a plurality of conductive traces formed in the die attach region and the conductive traces corresponding to the conductive terminals;
aligning the integrated circuit die and the substrate and bringing the plurality of conductive terminals and the conductive traces into contact, so that the solder depositions contact the conductive traces; and
selectively heating the integrated circuit die and the conductive terminals relative to the protected region of the substrate to a temperature sufficient to cause the solder depositions to melt and reflow, forming solder connections between the conductive traces on the substrate and the conductive terminals on the integrated circuit die.

### Claim 2 (depends on 1)

The method of claim 1, wherein during the selectively heating, the integrated circuit die reaches a temperature of at least 300 degrees Celsius.

### Claim 3 (depends on 2)

The method of claim 2, wherein during the selectively heating, the substrate does not exceed a temperature of 180 degrees Celsius.

### Claim 4 (depends on 1)

The method of claim 1, wherein during the selectively heating, infrared energy is applied to the integrated circuit die.

### Claim 5 (depends on 1)

The method of claim 1, wherein during the selectively heating, laser energy is applied to the integrated circuit die.

### Claim 6 (depends on 1)

The method of claim 1, wherein during the selectively heating, radio frequency energy is applied to the integrated circuit die.

### Claim 7 (depends on 1)

The method of claim 1, wherein receiving an integrated circuit die having a plurality of conductive terminals extending from a surface further comprises receiving an integrated circuit die with copper ladder bumps on the bond pads of the integrated circuit die.

### Claim 8 (depends on 1)

The method of claim 1, wherein receiving an integrated circuit die having a plurality of conductive terminals extending from a surface further comprises receiving an integrated circuit die having metal pillar bumps on the bond pads of the integrated circuit die.

### Claim 9 (depends on 1)

The method of claim 1, wherein providing a substrate having a die attach region on a surface for receiving the integrated circuit die comprises providing the substrate having a plurality of conductive traces formed in the die attach region, and forming cover material over the substrate in the protected region.

### Claim 10 (depends on 9)

The method of claim 9, and further comprising disposing a reflective coating over the cover material over the substrate, the reflective coating comprising a metal.

### Claim 11

A method, comprising:
providing a substrate core having a plurality of die attach regions on a die side surface each for receiving an integrated circuit, and having regions outside the die attach regions;
forming conductive traces on the substrate core, the conductive traces exposed in the die attach regions for coupling to conductive terminals of an integrated circuit die to be flip chip mounted in each die attach region;
receiving a plurality of integrated circuit dies, each having a plurality of conductive terminals for flip chip mounting to the substrate core, each conductive terminal having solder deposited on at least an end portion;
aligning an integrated circuit die of the plurality of integrated circuit dies with each die attach region on the substrate, and bringing the solder deposited on the end portion of the conductive terminals into physical contact with the conductive traces; and
performing a thermal reflow of the solder deposits by selectively heating the plurality of integrated circuit dies to a temperature sufficient to melt the solder deposits, without heating the substrate above a temperature of 180 degrees Celsius.

### Claim 12 (depends on 11)

The method of claim 11, wherein the selectively heating comprises exposing the integrated circuit dies to an energy source selected from the group consisting essentially of infrared, laser, and radio frequency energy sources.

### Claim 13 (depends on 11)

The method of claim 11, wherein providing the substrate core having a plurality of die attach regions on the die side surface further comprises providing cover material on the die side surface of the substrate outside of the die attach regions.

### Claim 14 (depends on 13)

The method of claim 13, and further comprising providing reflective material on the cover material.

### Claim 15 (depends on 14)

The method of claim 14, wherein performing the selectively heating comprises exposing the integrated circuit dies to infrared energy sources.

### Claim 16

A method, comprising:
forming a solder deposit on an least an end portion of a plurality of conductive terminals of each of a plurality of integrated circuit dies;
providing a substrate having die attach regions for flip chip mounting of the integrated circuit dies to a die side of the substrate, and having conductive traces disposed in the die attach regions and corresponding to the conductive terminals of the integrated circuit dies, and having cover material over the die side of the substrate outside of the die attach regions; and
disposing one of the plurality of integrated circuit dies in each die attach region, bringing the solder deposits into contact with the conductive traces and selectively heating the integrated circuit dies to melt the solder deposits, and forming an electrical connection and a physical solder connection between the conductive terminals and the conductive traces.

### Claim 17 (depends on 16)

The method of claim 16, wherein selectively heating comprises exposing the integrated circuit dies to an energy source that is one selected from the group consisting essentially of infrared, laser and radio frequency energy sources.

### Claim 18 (depends on 16)

The method of claim 16, wherein the conductive terminals comprise copper ladder bumps.

### Claim 19 (depends on 16)

The method of claim 16, wherein the conductive terminals comprise copper pillar bumps.

### Claim 20 (depends on 16)

The method of claim 16, wherein the conductive terminals further comprise copper and each of the conductive terminals has sidewalls covered with copper oxide material.