# US 2014/0193950 A1 · Electronic device package and fabrication method thereof

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- Number: US 2014/0193950 A1
- Document ID: US20140193950A1
- Status: Published application
- Kind: A1
- Application number: 14/207,247
- Filed: 2014-03-12
- Published: 2014-07-10
- Earliest claimed: 2010-03-26
- Assignees: Xintec Inc.
- Applicants: Xintec Inc.
- Inventors: Shu-Ming CHANG; Bai-Yao LOU; Ying-Nan WEN; Chien-Hung LIU
- Web page: https://patentgrep.com/patent/US20140193950A1

## CPC

- H10W 95/00: Packaging processes not covered by the other groups of this subclass
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/216: {characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes}
- H10H 20/857: Interconnections, e.g. lead-frames, bond wires or solder balls
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/66: Conductive materials thereof
- H10W 70/69: Insulating materials thereof
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01215: {forming coatings}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01255: {by using masks}
- H10W 72/019: {of bond pads}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01955: {by using masks}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07353: {changes in shapes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/255: {of outermost layers of multilayered bumps, e.g. material of a coating}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/332: {Plan-view shape, i.e. in top view}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS

## Abstract

An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed.

## Claims

### Claim at position 1

1-10. (canceled)

### Claim 11

A method for fabricating an electronic device package, comprising:
providing at least one semiconductor chip having a first surface and a second surface opposite thereto, wherein the semiconductor chip has at least one via opening therein, which extends to the first surface, and has at least one conductive pad structure disposed on the bottom of the via opening;
attaching the second surface of the semiconductor chip onto a substrate;
forming at least one redistribution layer on the first surface of the semiconductor chip and electrically connected to the conductive pad structure through the via opening;
covering the first surface of the semiconductor chip with a sacrificial pattern layer, wherein the sacrificial pattern layer has an opening to partially expose the redistribution layer;
forming an abut portion in the opening, wherein the abut portion electrically contacts the exposed redistribution layer;
removing the sacrificial pattern layer; and
covering the first surface of the semiconductor chip with a passivation layer, such that the passivation layer surrounds the abut portion.

### Claim 12 (depends on 11)

The method of claim 11, wherein after formation of the abut portion and removal of the sacrificial pattern layer, the method further comprises a step of forming a conductive protection layer on the surface of the abut portion.

### Claim 13 (depends on 12)

The method of claim 12, wherein the sacrificial pattern layer comprises a dry film or a wet resist.

### Claim 14 (depends on 11)

The method of claim 11, wherein the abut portion comprises the same material as that of the redistribution layer.

### Claim 15 (depends on 11)

The method of claim 11, wherein the abut portion protrudes from an upper surface of the passivation layer and a gap is between the abut portion and the passivation layer.

### Claim 16 (depends on 11)

The method of claim 11, wherein the passivation layer partially covers an upper surface of the abut portion.

### Claim 17 (depends on 11)

The method of claim 11, wherein an upper surface of the passivation layer is not lower than that of the abut portion and is in direct contact with the sidewalls of the abut portions.

### Claim 18 (depends on 17)

The method of claim 17, wherein the abut portion comprises copper, nickel, gold, solder materials or combinations thereof and is formed by plating.

### Claim 19 (depends on 18)

The method of claim 18, further forming a seed layer is between the redistribution layer and the conductive pad structure.

### Claim 20 (depends on 11)

The method of claim 11, wherein the passivation layer comprises light-sensitive or non-light-sensitive solder mask materials.