# US 2014/0193948 A1 · Integrated bondline spacers for wafer level packaged circuit devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0193948 A1 - Document ID: US20140193948A1 - Status: Published application - Kind: A1 - Application number: 14/202,756 - Filed: 2014-03-10 - Published: 2014-07-10 - Earliest claimed: 2012-11-02 - Assignees: Raytheon Company - Applicants: Raytheon Company - Inventors: Roland Gooch; Buu Diep; Thomas Allan Kocian; Stephen H. Black; Adam M. Kennedy - Web page: https://patentgrep.com/patent/US20140193948A1 ## CPC - B81B 7/0041: {maintaining a controlled atmosphere with techniques not provided for in B81B7/0038} - B81B 7/007: {Interconnections between the MEMS and external electrical signals} - B81C 1/00269: {Bonding of solid lids or wafers to the substrate} - H10W 76/15: Containers comprising an insulating or insulated base - B81C 2203/019: characterised by the material or arrangement of seals between parts - H10W 72/01335: {by plating, e.g. electroless plating or electroplating} - H10W 72/01338: {in gaseous form, e.g. by CVD or PVD} - H10W 72/073: {of die-attach connectors} - H10W 72/07302: {using an auxiliary member} - H10W 72/07304: {the auxiliary member being temporary, e.g. a sacrificial coating} - H10W 72/07327: {involving guiding structures, e.g. spacers or supporting members} - H10W 72/331: {Shapes of die-attach connectors} - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 76/60: Seals - B81B: MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES (piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/00, H10N35/00) - B81C: PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS (making microcapsules or microballoons B01J13/02; processes or apparatus specially adapted for the manufacture or treatment of piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/01) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer. ## Claims ### Claim 1 A method of forming a wafer level packaged circuit device, the method comprising: forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer. ### Claim 2 (depends on 1) The method of claim 1, wherein: the first group of one or more material layers are materials that are used to form one or more of: an integrated circuit and a sealing ring for the device wafer; and the second group of one or more material layers are materials that are used to form one or more of: an antireflective coating and a sealing ring for the cap wafer. ### Claim 3 (depends on 2) The method of claim 2, wherein the first group of one or more material layers further comprises: a polyimide layer formed on the substrate of the device wafer; and a solder metal stack layer formed on the polyimide layer. ### Claim 4 (depends on 3) The method of claim 3, wherein the solder metal stack layer comprises a titanium/nickel/gold stack layer. ### Claim 5 (depends on 2) The method of claim 2, wherein the second group of one or more material layers further comprises: an antireflective coating layer formed on the substrate of the device wafer; and a solder metal stack layer formed on the antireflective coating layer. ### Claim 6 (depends on 5) The method of claim 5, wherein the solder metal stack layer comprises a titanium/nickel/gold stack layer. ### Claim 7 (depends on 5) The method of claim 5, wherein the second group of one or more material layers further comprises a vacuum getter layer formed atop the solder metal layer stack layer. ### Claim 8 (depends on 7) The method of claim 7, wherein the vacuum getter layer comprises one or more of titanium, zirconium, iron, and vanadium. ### Claim 9 (depends on 1) The method of claim 1, further comprising bonding the cap wafer to the device wafer to define the integrated bond gap control structure (BGCS). ### Claim 10 (depends on 9) The method of claim 9, wherein the integrated BGCS has a thickness on the order of about 10 microns (um). ### Claim 11 (depends on 1) The method of claim 1, wherein the first region corresponds to a scribe region of the device wafer and the second region corresponds to a scribe region of the cap wafer. ### Claim 12 A method of forming a wafer level packaged circuit device, the method comprising: forming a device wafer, the device wafer including a polyimide layer formed in a first region of a substrate of the device wafer, and a first solder metal stack layer formed on the polyimide layer, wherein the polyimide layer is a same polyimide layer that is also used in the formation of microelectromechanical systems (MEMS) devices of an integrated circuit on the device wafer, and the first solder metal stack layer is also a same first solder metal stack layer used to form a sealing ring for the device wafer; forming a cap wafer, the cap wafer including an antireflective coating layer formed in a second region of a substrate of the cap wafer, and a second solder metal stack layer formed on the antireflective coating layer, wherein the antireflective coating layer is a same antireflective coating layer that is also formed on a cavity portion of the cap wafer, and the second solder metal stack layer is also a same second solder metal stack layer used to form a sealing ring for the cap wafer; and bonding the cap wafer to the device wafer, thereby defining an integrated bond gap control structure comprising the polyimide layer, the first solder metal stack layer, the second solder metal stack layer, and the antireflective coating layer. ### Claim 13 (depends on 12) The method of claim 12, wherein: forming the cap wafer further comprises forming a vacuum getter layer on the second solder metal stack layer, wherein the vacuum getter layer is a same vacuum getter layer that is also formed on the antireflective coating layer of the cavity portion of the cap wafer; and wherein the integrated bond gap control structure comprises the polyimide layer, the first solder metal stack layer, the vacuum getter layer, the second solder metal stack layer, and the antireflective coating layer. ### Claim 14 (depends on 13) The method of claim 13, wherein the first and solder metal stack layers comprise a titanium/nickel/gold stack layers. ### Claim 15 (depends on 13) The method of claim 13, wherein the integrated bond gap control structure has a thickness on the order of about 10 microns (um). ### Claim 16 (depends on 13) The method of claim 13, wherein: the polyimide layer has a thickness on the order of about 1.0 microns (μm) to about 2.0 μm; the first solder metal stack layer has a thickness on the order of about 0.4 μm to about 0.8 μm; the vacuum getter layer has a thickness on the order of about 0.3 μm to about 2.0 μm; the second solder metal stack layer has a thickness on the order of about 0.4 μm to about 0.8 μm; and the antireflective coating layer has a thickness on the order of about 5.5 μm to about 8.0 μm. ### Claim 17 (depends on 12) The method of claim 12, wherein the first region corresponds to a scribe region of the device wafer and the second region corresponds to a scribe region of the cap wafer. ### Claim 18 A method of forming a wafer level packaged circuit device, the method comprising: forming a device wafer; forming a cap wafer; forming, on either the cap wafer or the device wafer, a bond gap control structure comprising one or more material layers used in the formation of either the cap wafer or the device wafer, and left remaining in a region of a substrate of either the cap wafer or the device wafer; and bonding the cap wafer to the device wafer. ### Claim 19 (depends on 18) The method of claim 18, wherein the bond gap control structure is formed on the cap layer, and further comprises one or more of: a vacuum getter layer, a solder metal stack layer, and an antireflective coating layer. ### Claim 20 (depends on 18) The method of claim 18, wherein the bond gap control structure is formed on the wafer layer, and further comprises one or more of: a solder metal stack layer, and a polyimide layer.