# US 2014/0192940 A1 · Communication channel calibration for drift conditions

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- Number: US 2014/0192940 A1
- Document ID: US20140192940A1
- Status: Published application
- Kind: A1
- Application number: 14/201,778
- Filed: 2014-03-07
- Published: 2014-07-10
- Earliest claimed: 2004-01-28
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Frederick A. Ware; Richard E. Perego; Craig E. Hampel
- Web page: https://patentgrep.com/patent/US20140192940A1

## CPC

- H04L 7/0016: {correction of synchronization errors}
- H04L 7/0087: {Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection}
- H04L 7/0091: {Transmitter details}
- H04L 7/10: Arrangements for initial synchronisation
- H04L 25/0292: {Arrangements specific to the receiver end}
- H04L 25/12: Compensating for variations in line impedance
- G11C 7/04: with means for avoiding disturbances due to temperature effects
- G11C 2207/2254: Calibration
- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

## Claims

### Claim 1

A memory controller integrated circuit, comprising:
a receiver to sample data arriving at the memory controller integrated circuit from a memory device, the receiver to sample the data at a sampling instant;
logic to establish an operational value for the sampling instant, wherein the operational value is established during a calibration phase; and
logic to compensate for drift between the operational value and timing associated with the data, and to update the operational value for the sampling instant in response to drift detected subsequent to establishment of the operational value.

### Claim 2 (depends on 1)

The memory controller integrated circuit of claim 1, wherein the logic to establish the operational value includes logic to vary the sampling instant, while the receiver is to sample the data, to responsively identify a data window, and logic to establish the operational value dependent on timing of the data window.

### Claim 3 (depends on 2)

The memory controller integrated circuit of claim 2, wherein:
the logic to establish the operational value includes logic to transmit a symbol pattern to the memory device during the calibration phase;
the receiver is to, during the calibration phase, sample a sequence of values received back from the memory device;
the logic to establish the operational value includes logic is to compare the symbol pattern and the sequence to detect mismatch; and
the logic to vary the sampling instant to identify the data window is to identify the data window dependent on detected mismatch.

### Claim 4 (depends on 3)

The memory controller integrated circuit of claim 3, wherein the logic to establish the operational value includes a pseudorandom bit pattern generator, and where the data pattern comprises a pseudorandom bit pattern of at least 27−1 bits.

### Claim 5 (depends on 1)

The memory controller integrated circuit of claim 1, wherein the logic to establish the operational value for the sampling instant is to detect occurrence of at least one edge, at the receiver, associated with a transition between data values, and to establish the operational value for the sampling instant dependent on timing of the at least one edge.

### Claim 6 (depends on 5)

The memory controller integrated circuit of claim 5, wherein the logic to establish the operational value for the sampling instant is to detect occurrence of two different edges, at the receiver, associated with a data symbol period of data received at the receiver, and to establish the operational value for the sampling instant dependent on timing of each of the two different edges.

### Claim 7 (depends on 6)

The memory controller integrated circuit of claim 6, wherein the logic to establish the operational value for the sample instant is to establish the operational value for the sampling instant at an approximate center point between timing of the two different edges.

### Claim 8 (depends on 7)

The memory controller integrated circuit of claim 7, wherein the logic to compensate for drift and update the operational value includes logic to periodically identify variation in a timing point associated with the data induced by temperature change and to update the operational value to track said variation.

### Claim 9

A memory controller integrated circuit, comprising:
a receiver to sample data arriving at the memory controller integrated circuit from a memory device, the receiver to sample the data at a sampling instant;
logic to establish an operational value for the sampling instant, wherein the operational value is established during a calibration phase; and
logic to compensate for drift between the operational value and timing associated with the data, and to update the operational value for the sampling instant in response to the drift detected after establishment of the operational value;
wherein the logic to establish the operational value is to detect occurrence of at least one edge, at the receiver, associated with a transition between data values received during the calibration phase, and to establish the operational value for the sampling instant dependent on timing of the at least one edge.

### Claim 10 (depends on 9)

The memory controller integrated circuit of claim 9, wherein the logic to compensate for drift and update the operational value includes logic to periodically identify variation in a timing point associated with the data and to update the operational value to track said variation.

### Claim 11 (depends on 9)

The memory controller integrated circuit of claim 9, wherein the logic to establish the operational value for the sampling instant is to detect occurrence of two different edges, at the receiver, associated with a data symbol period of data received at the receiver, and to establish the operational value for the sampling instant dependent on timing of the two different edges.

### Claim 12 (depends on 11)

The memory controller integrated circuit of claim 11, wherein the logic to establish the operational value for the sample instant is to establish the operational value for the sampling instant at an approximate center point between timing of the two different edges.

### Claim 13 (depends on 9)

The memory controller integrated circuit of claim 9, wherein the logic to establish the operational value includes logic to vary the sampling instant, while the receiver is to sample the data, to responsively identify a data window, and logic to establish the operational value dependent on timing of the data window.

### Claim 14 (depends on 13)

The memory controller integrated circuit of claim 13, wherein:
the logic to establish the operational value includes logic to transmit a symbol pattern to the memory device during the calibration phase;
the receiver is to, during the calibration phase, sample a sequence of values received back from the memory device;
the logic to establish the operational value includes logic is to compare the symbol pattern and the sequence to detect mismatch; and
the logic to vary the sampling instant to identify the data window is to identify the data window dependent on detected mismatch.

### Claim 15 (depends on 13)

The memory controller integrated circuit of claim 13, wherein the logic to establish the operational value includes a pseudorandom bit pattern generator, and where the symbols comprise a pseudorandom bit pattern of at least 27−1 bits.

### Claim 16

A method of operating a memory controller integrated circuit, comprising:
sampling data arriving at the memory controller integrated circuit from a memory device according to sampling instant;
establishing an operational value for the sampling instant, wherein the operational value is established during a calibration phase; and
compensating for drift between the operational value and timing associated with the data, and updating the operational value for the sampling instant in response to drift detected subsequent to establishment of the operational value.

### Claim 17 (depends on 16)

The method of claim 16, wherein establishing the operational value includes varying the sampling instant, while sampling the data, to responsively identify a data window, and establishing the operational value dependent on timing of the data window.

### Claim 18 (depends on 17)

The method of claim 17, wherein:
establishing the operational value includes transmitting a symbol pattern to the memory device during the calibration phase;
sampling, during the calibration phase, a sequence of values received back from the memory device;
establishing the operational value includes comparing the symbol pattern and the sequence to detect mismatch; and
identifying the data window is to identify the data window dependent on detected mismatch.

### Claim 19 (depends on 16)

The method of claim 16, wherein establishing the operational value for the sampling instant includes detecting occurrence of at least one edge, at the memory controller integrated circuit, associated with a transition between data values, and establishing the operational value for the sampling instant dependent on timing of the at least one edge.

### Claim 20 (depends on 16)

The method of claim 16, wherein compensating for drift and updating the operational value includes periodically identifying variation in a timing point associated with the data induced by temperature change and to updating the operational value to track said variation.