# US 2014/0192938 A1 · Signal processing circuit and signal processing method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0192938 A1 - Document ID: US20140192938A1 - Status: Published application - Kind: A1 - Application number: 14/066,774 - Filed: 2013-10-30 - Published: 2014-07-10 - Earliest claimed: 2013-01-09 - Assignees: Fujitsu Limited - Applicants: Fujitsu Limited - Inventors: Hirotaka TAMURA - Web page: https://patentgrep.com/patent/US20140192938A1 ## CPC - H04L 7/0041: {Delay of data signal} - H03K 5/00: Manipulating of pulses not covered by one of the other main groups of this subclass (circuits with regenerative action H03K3/00, H03K4/00; by the use of non-linear magnetic or dielectric devices H03K3/45) - H03M 1/1215: {using time-division multiplexing} - H03M 9/00: Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) - H03K 2005/00104: {using a reference signal, e.g. a reference clock} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A signal processing circuit includes: a delay line configured to output, to a plurality of taps, signals with different delay times obtained by delaying an input signal, respectively; and a plurality of synchronization circuits configured to sample the signals from the plurality of taps in a phase in synchronization with a clock signal, wherein each of the plurality of synchronization circuits samples a sample signal from one of the plurality of taps in different phases and outputs a plurality of output signals. ## Claims ### Claim 1 A signal processing circuit comprising: a delay line configured to output, to a plurality of taps, signals with different delay times obtained by delaying an input signal, respectively; and a plurality of synchronization circuits configured to sample the signals from the plurality of taps in a phase in synchronization with a clock signal, wherein each of the plurality of synchronization circuits samples a sample signal from one of the plurality of taps in different phases and outputs a plurality of output signals. ### Claim 2 (depends on 1) The signal processing circuit according to claim 1, wherein a cycle of the clock signal is longer than a maximum value of the delay times. ### Claim 3 (depends on 1) The signal processing circuit according to claim 1, wherein the plurality of synchronization circuits include: first synchronization circuits, coupled to the plurality of taps, configured to sample the sample signal in a first phase; and second synchronization circuits, coupled to the plurality of taps, configured to sample the sample signal in a second phase, which is different from the first phase. ### Claim 4 (depends on 1) The signal processing circuit according to claim 1, wherein the plurality of synchronization circuits output a first signal having a first level when the signals from the plurality of taps are larger than a threshold or output a second signal having a second level when the signals from the plurality of taps are smaller than the threshold. ### Claim 5 (depends on 1) The signal processing circuit according to claim 1, wherein the plurality of synchronization circuits sample the signals from the plurality of taps, output sampled signals and include a plurality of analog-digital converters that perform analog-to-digital conversion of the sampled signals. ### Claim 6 (depends on 5) The signal processing circuit according to claim 5, wherein each of the plurality of analog-digital converters performs analog-to-digital conversion of a sampled signal from one of the plurality of synchronization circuits in synchronization with the different phases and outputs the plurality of output signals. ### Claim 7 (depends on 1) The signal processing circuit according to claim 1, further comprising: a plurality of oscillators, coupled to each other, configured to distribute the clock signal to the plurality of synchronization circuits. ### Claim 8 (depends on 1) The signal processing circuit according to claim 1, further comprising: an adjusting circuit configured to detect a deviation between phases of the plurality of output signals and adjusts the delay time of the delay line according to the detected deviation between the phases. ### Claim 9 (depends on 1) The signal processing circuit according to claim 1, further comprising: a predicted value output circuit configured to detect a difference between phases of the plurality of output signals and outputs a predicted value of phases of the plurality of output signals according to the detected difference between phases. ### Claim 10 (depends on 8) The signal processing circuit according to claim 8, wherein the adjusting circuit adjusts the delay time of the delay line according to a deviation between a phase of an output signal of one of the synchronization circuits that corresponds to a tap with a minimum delay time and a phase of an output signal of one of the synchronization circuits that corresponds to a tap with a maximum delay time. ### Claim 11 A signal processing method comprising: delaying an analog signal via a delay line including delay elements and outputting analog signals with different delay times to a plurality of taps; sampling a signal from a first tap among the plurality of taps in a first phase that is in synchronization with a clock signal and outputting the first sampled signal; and sampling the signal from the first tap in a second phase that is in synchronization with the clock signal and outputting the second sampled signal.