# US 2014/0192929 A1 · Method and apparatus for clock data recovery from manchester coded serial data stream > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0192929 A1 - Document ID: US20140192929A1 - Status: Published application - Kind: A1 - Application number: 13/737,055 - Filed: 2013-01-09 - Published: 2014-07-10 - Earliest claimed: 2013-01-09 - Assignees: Rockwell Automation Technologies, Inc. - Inventors: Darshini H. Mehta; Alan Campbell - Web page: https://patentgrep.com/patent/US20140192929A1 ## CPC - H04L 7/0338: {the correction of the phase error being performed by a feed forward loop} - H04L 7/0066: {detection of error based on transmission code rule} - H04L 25/4904: {using self-synchronising codes, e.g. split-phase codes} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Methods and apparatus are presented for obtaining clock data from Manchester coded serial data streams, in which received data is sampled at a sample rate higher than the serial data baud rate, multi-bit groups of transition bits are generated which individually indicate data transition locations in a corresponding multi-bit sampled data bit group, and clock data is derived using the multi-bit groups of transition bits without requiring receipt of synchronization data or receipt of a separate clock. ## Claims ### Claim 1 A method for deriving clock data from a Manchester coded serial data stream, the method comprising: receiving a Manchester coded serial data stream corresponding to an input baud rate; sampling the Manchester coded serial data stream at a sample rate higher than the input baud rate to obtain multi-bit groups of sampled bits; constructing multi-bit groups of transition bits, the multi-bit groups of transition bits individually indicating data transition locations in a corresponding multi-bit group of sampled bits; and deriving clock data based solely on the multi-bit groups of transition bits. ### Claim 2 (depends on 1) The method of claim 1, wherein sampling the Manchester coded serial data stream comprises quadrature sampling the Manchester coded serial data stream to obtain 4-bit groups of sampled bits, and wherein constructing multi-bit groups of transition bits comprises constructing 4-bit groups of transition bits individually indicating data transition locations a corresponding 4-bit group of sampled bits. ### Claim 3 (depends on 1) The method of claim 1, comprising: detecting at least one pattern in the multi-bit groups of transition bits; and deriving the clock data based on the at least one pattern in the multi-bit groups of transition bits. ### Claim 4 (depends on 3) The method of claim 3, wherein deriving the clock data comprises: selectively generating clock data edges in the clock data based at least partially on transitions identified as mid-bits associated with transitions between received data bits; and identifying a given transition in a current multi-bit group of transition bits as a mid-bit if no transitions occurred in the two previous multi-bit groups of transition bits. ### Claim 5 (depends on 4) The method of claim 4, wherein deriving the clock data comprises identifying a given transition in a current multi-bit group of transition bits as a mid-bit if a transition is indicated in a most significant bit in a second previous multi-bit group of transition bits and a transition is indicated in a least significant bit in the current multi-bit group of transition bits. ### Claim 6 (depends on 3) The method of claim 3, wherein deriving the clock data comprises: selectively generating clock data edges in the clock data based at least partially on transitions identified as mid-bits associated with transitions between received data bits; and identifying a given transition in a current multi-bit group of transition bits as a mid-bit if a transition is indicated in a most significant bit in a second previous multi-bit group of transition bits and a transition is indicated in a least significant bit in the current multi-bit group of transition bits. ### Claim 7 A computer readable medium with computer executable instructions for deriving clock data from a Manchester coded serial data stream, the computer readable medium comprising computer executable instructions for: receiving a Manchester coded serial data stream corresponding to an input baud rate; sampling the Manchester coded serial data stream at a sample rate higher than the input baud rate to obtain multi-bit groups of sampled bits; constructing multi-bit groups of transition bits, the multi-bit groups of transition bits individually indicating data transition locations in a corresponding multi-bit group of sampled bits; and deriving clock data based solely on the multi-bit groups of transition bits. ### Claim 8 A receiver for processing a Manchester coded serial data stream, the receiver comprising: a sampling circuit operative to sample the Manchester coded serial data stream at a sample rate higher than the input baud rate to obtain multi-bit groups of sampled bits; a transition circuit operative to generate multi-bit groups of transition bits, the individual groups of transition bits indicating data transition locations in a corresponding multi-bit group of sampled bits; and a clock data recovery circuit operative to generate clock data based solely on the multi-bit groups of transition bits. ### Claim 9 (depends on 8) The receiver of claim 8, wherein the clock data recovery circuit comprises a logic circuit operative to detect at least one pattern in the multi-bit groups of transition bits, and to derive the clock data based on the at least one pattern in the multi-bit groups of transition bits. ### Claim 10 (depends on 9) The receiver of claim 9, wherein the logic circuit is operative to selectively generate clock data edges in the clock data based at least partially on transitions identified as mid-bits associated with transitions between received data bits, and to identify a given transition in a current multi-bit group of transition bits as a mid-bit if no transitions occurred in the two previous multi-bit groups of transition bits. ### Claim 11 (depends on 10) The receiver of claim 10, wherein the logic circuit is operative to identify a given transition in a current multi-bit group of transition bits as a mid-bit if a transition is indicated in a most significant bit in a second previous multi-bit group of transition bits and a transition is indicated in a least significant bit in the current multi-bit group of transition bits. ### Claim 12 (depends on 9) The receiver of claim 9, wherein the logic circuit is operative to selectively generate clock data edges in the clock data based at least partially on transitions identified as mid-bits associated with transitions between received data bits, and to identify a given transition in a current multi-bit group of transition bits as a mid-bit if a transition is indicated in a most significant bit in a second previous multi-bit group of transition bits and a transition is indicated in a least significant bit in the current multi-bit group of transition bits. ### Claim 13 A motor drive, comprising: power conversion circuitry operative to receive input power from a power source and to provide output power to drive a motor load; and a receiver for processing a Manchester coded serial data stream received by the motor drive, the receiver comprising: a sampling circuit operative to sample the Manchester coded serial data stream at a sample rate higher than the input baud rate to obtain multi-bit groups of sampled bits; a transition circuit operative to generate multi-bit groups of transition bits, the individual groups of transition bits indicating data transition locations in a corresponding multi-bit group of sampled bits; and a clock data recovery circuit operative to generate clock data based solely on the multi-bit groups of transition bits. ### Claim 14 (depends on 13) The motor drive of claim 13, wherein the clock data recovery circuit comprises a logic circuit operative to detect at least one pattern in the multi-bit groups of transition bits, and to derive the clock data based on the at least one pattern in the multi-bit groups of transition bits. ### Claim 15 (depends on 14) The motor drive of claim 14, wherein the logic circuit is operative to selectively generate clock data edges in the clock data based at least partially on transitions identified as mid-bits associated with transitions between received data bits, and to identify a given transition in a current multi-bit group of transition bits as a mid-bit if no transitions occurred in the two previous multi-bit groups of transition bits. ### Claim 16 (depends on 15) The motor drive of claim 15, wherein the logic circuit is operative to identify a given transition in a current multi-bit group of transition bits as a mid-bit if a transition is indicated in a most significant bit in a second previous multi-bit group of transition bits and a transition is indicated in a least significant bit in the current multi-bit group of transition bits. ### Claim 17 (depends on 14) The motor drive of claim 14, wherein the logic circuit is operative to selectively generate clock data edges in the clock data based at least partially on transitions identified as mid-bits associated with transitions between received data bits, and to identify a given transition in a current multi-bit group of transition bits as a mid-bit if a transition is indicated in a most significant bit in a second previous multi-bit group of transition bits and a transition is indicated in a least significant bit in the current multi-bit group of transition bits.