# US 2014/0192797 A1 · Systems and methods for transporting a clock signal over a network > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0192797 A1 - Document ID: US20140192797A1 - Status: Published application - Kind: A1 - Application number: 14/150,698 - Filed: 2014-01-08 - Published: 2014-07-10 - Earliest claimed: 2013-01-08 - Assignees: Aviat U.S., Inc. - Applicants: Aviat U.S., Inc. - Inventors: Sergio Licardie; Ivana Maric - Web page: https://patentgrep.com/patent/US20140192797A1 ## CPC - H04J 3/0658: {Clock or time synchronisation among packet nodes} - H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S) ## Abstract According to some embodiments, a master device sends synchronization packets to one or more slave devices, and does so periodically based on a master clock signal having a master clock frequency. At each of the slave devices, an algorithm estimates the master clock frequency based on the timing of synchronization packet arrivals the slave device. The algorithm may estimate the master clock frequency using both the currently-observed timing of synchronization packet arrivals and the history of previous synchronization packet arrivals (e.g., previously-observed timing of synchronization packet arrivals). Based on the estimated master clock frequency, each of the one or more slave devices can update the frequency of their respective slave clock signal (e.g., using a frequency offset) to match that of the estimated master clock frequency. ## Claims ### Claim 1 A system comprising: a clock module configured to provide a master clock signal having a master clock frequency; a counter module configured to increment or decrement a counter value based on the master clock signal; a packet generation module configured to monitor the counter value and to generate a synchronization packet when the counter value satisfies a condition; and a communication module configured to transmit the synchronization packet to a slave device. ### Claim 2 (depends on 1) The system of claim 1, wherein the condition includes the counter value reaching a predefined threshold. ### Claim 3 (depends on 1) The system of claim 1, wherein the clock module is further configured to synchronize the master clock signal based on a primary reference clock. ### Claim 4 (depends on 3) The system of claim 3, wherein the primary reference clock includes a Synchronous Ethernet (SyncE) reference clock. ### Claim 5 (depends on 1) The system of claim 1, wherein the system is included in a split-mount microwave system. ### Claim 6 A system comprising: a packet monitoring module configured to detect receipt of a synchronization packet from a master device; a clock module configured to provide a slave clock signal having a slave clock frequency; a counter module configured to increment or decrement a counter value based on the slave clock signal; a clock frequency estimation module configured to, in response to the packet monitoring module detecting receipt of the synchronization packet from the master device, obtain a current counter value from the counter module and to determine an estimated clock frequency of the master device based on the current counter value; and a frequency offset calculation module configured to calculate a frequency offset for the slave clock frequency based on the estimated clock frequency of the master device. ### Claim 7 (depends on 6) The system of claim 6, wherein the clock module is further configured to update the slave clock frequency based on the frequency offset. ### Claim 8 (depends on 7) The system of claim 7, wherein the system is included in a split-mount microwave system configured to receive the synchronization packet from the master device. ### Claim 9 (depends on 7) The system of claim 7, wherein the clock frequency estimation module is further configured to determine the estimated clock frequency of the master device based further on a previously estimated clock frequency of the master device. ### Claim 10 (depends on 9) The system of claim 9, wherein the clock frequency estimation module is further configured to determine the estimated clock frequency of the master device using a Kalman filter. ### Claim 11 A method comprising: monitoring a counter value of a counter at a master device, the counter being driven by a master clock signal having a master clock frequency; generating a synchronization packet in response to the counter value satisfying a condition; and transmitting the synchronization packet from the master device to a slave device in response to satisfaction of the condition. ### Claim 12 (depends on 11) The method of claim 11, wherein the condition includes the counter value reaching a predefined threshold. ### Claim 13 (depends on 11) The method of claim 11, wherein the master device includes a master clock configured to provide the master clock signal. ### Claim 14 (depends on 13) The method of claim 13, further comprising synchronizing the master clock signal based on a primary reference clock. ### Claim 15 (depends on 14) The method of claim 14, wherein the primary reference clock includes a Synchronous Ethernet (SyncE) reference clock. ### Claim 16 (depends on 11) The method of claim 11, wherein the transmitting the synchronization packet from the master device to the slave device comprises transmitting the synchronization packet through a split-mount microwave transmitter. ### Claim 17 A method comprising: detecting receipt of a synchronization packet from a master device at a slave device; in response to the detecting the receipt of the synchronization packet at the slave device, obtaining a current counter value of a counter at the slave device, the counter being driven by a slave clock signal having a slave clock frequency; generating an estimated clock frequency for the master device based on the current counter value; and calculating a frequency offset based on the slave clock frequency and the estimated clock frequency of the master device. ### Claim 18 (depends on 17) The method of claim 17, further comprising updating the slave clock frequency based on the frequency offset. ### Claim 19 (depends on 17) The method of claim 17, further comprising receiving the synchronization packet through a split-mount microwave receiver. ### Claim 20 (depends on 17) The method of claim 17, wherein the slave device includes a slave clock configured to provide the slave clock signal. ### Claim 21 (depends on 17) The method of claim 17, wherein the generating the estimated clock frequency for the master device is further based on a previously estimated clock frequency for the master device. ### Claim 22 (depends on 21) The method of claim 21, wherein the generating the estimated clock frequency for the master device comprises by using a Kalman filter. ### Claim 23 A system comprising: means for monitoring a counter value of a counter at a master device, the counter being driven by a master clock signal having a master clock frequency; means for generating a synchronization packet in response to the counter value satisfying a condition; and means for transmitting the synchronization packet from the master device to a slave device. ### Claim 24 A system comprising: means for detecting receipt of a synchronization packet from a master device at a slave device; means for obtaining a current counter value of a counter at the slave device in response to the detecting the receipt of the synchronization packet at the slave device, the counter being driven by a slave clock signal having a slave clock frequency; means for generating an estimated clock frequency of the master device based on the current counter value; and means for calculating a frequency offset based on the slave clock frequency and the estimated clock frequency of the master device.