# US 2014/0192607 A1 · Adaptive voltage input to a charge pump > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0192607 A1 - Document ID: US20140192607A1 - Status: Published application - Kind: A1 - Application number: 13/976,791 - Filed: 2012-05-08 - Published: 2014-07-10 - Earliest claimed: 2012-05-08 - Assignees: Intel Corporation - Inventors: Kuljit Bains; George Vergis - Web page: https://patentgrep.com/patent/US20140192607A1 ## CPC - G11C 5/145: {Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence)} - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 29/021: {in voltage or current generators} - G11C 29/028: {with adaption or trimming of parameters} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory subsystem includes an adaptive output voltage to provide a voltage based on a power profile of a memory device of the memory subsystem. A charge pump increases the voltage to a level needed to write data to the memory device. The voltage provided is based on the power profile of the memory device, which indicates a voltage level that provides good efficiency for the charge pump, and is within maximum levels for the memory device. The voltage can be higher than a nominal voltage indicated for the memory device in a specification. ## Claims ### Claim 1 A memory subsystem comprising: a memory device to store data, the memory device to receive an input voltage at a first voltage level, wherein writing data to the memory device uses a second voltage level higher than the first voltage level; a charge pump to increase the input voltage from the first voltage level to the second voltage level; and an adaptive voltage supply to provide the first voltage level based on a power profile of the memory device, the power profile indicating a maximum input voltage level for the memory device. ### Claim 2 (depends on 1) The memory subsystem of claim 1, wherein the memory device comprises a dynamic random access memory (DRAM) device. ### Claim 3 (depends on 1) The memory subsystem of claim 1, wherein the charge pump is to lower a duty cycle of a switch based on the first voltage level. ### Claim 4 (depends on 1) The memory subsystem of claim 1, wherein the adaptive voltage supply is to provide the first voltage at a level higher than a nominal voltage level indicated by a specification for the memory device. ### Claim 5 (depends on 4) The memory subsystem of claim 4, wherein the first voltage at the level higher than the nominal voltage level comprises a voltage level that is a tolerance amount lower than the maximum voltage level for the memory device. ### Claim 6 (depends on 5) The memory subsystem of claim 5, wherein the tolerance amount comprises a tolerance amount computed based on a reactive component of the power profile for the memory device. ### Claim 7 (depends on 1) The memory subsystem of claim 1, wherein the adaptive voltage supply further comprises a variable voltage divider. ### Claim 8 (depends on 7) The memory subsystem of claim 7, wherein the adaptive voltage supply further comprises a digitally controlled voltage level. ### Claim 9 (depends on 8) The memory subsystem of claim 8, wherein the adaptive voltage supply further comprises a digital to analog converter. ### Claim 10 An electronic device comprising: a memory subsystem having a memory device to store data, the memory device to receive an input voltage at a first voltage level, wherein writing data to the memory device uses a second voltage level higher than the first voltage level; a charge pump to increase the input voltage from the first voltage level to the second voltage level; and an adaptive voltage supply to provide the first voltage level based on a power profile of the memory device, the power profile indicating a maximum input voltage level for the memory device; and a multicore processor coupled to the memory subsystem to access the memory subsystem during execution of the processor. ### Claim 11 (depends on 10) The device of claim 10, wherein the memory device comprises a dynamic random access memory (DRAM) device. ### Claim 12 (depends on 10) The device of claim 10, wherein the charge pump is to lower a duty cycle of a switch based on the first voltage level. ### Claim 13 (depends on 10) The device of claim 10, wherein the adaptive voltage supply is to provide the first voltage at a level higher than a nominal voltage level indicated by a specification for the memory device, the higher level being a voltage level that is a tolerance amount lower than the maximum input voltage for the memory device. ### Claim 14 (depends on 13) The device of claim 13, wherein the tolerance amount comprises a tolerance amount computed based on a reactive component of the power profile for the memory device. ### Claim 15 (depends on 10) The device of claim 10, wherein the adaptive voltage supply further comprises a digitally controlled variable voltage divider. ### Claim 16 A method comprising: receiving an input voltage at a voltage regulator; determining a power profile of a memory device coupled to the voltage regulator; adjusting an output voltage of the voltage regulator based on the power profile; and providing the adjusted output voltage to a charge pump of the memory device, wherein the charge pump is to increase the output voltage to a stepped-up voltage level used for writing data to the memory device. ### Claim 17 (depends on 16) The method of claim 16, further comprising decreasing a duty cycle of a switch of the charge pump based on the adjusted output voltage. ### Claim 18 (depends on 16) The method of claim 16, wherein adjusting the output voltage comprises adjusting the output voltage to a level higher than a nominal voltage level indicated by a specification for the memory device, and a tolerance amount lower than the maximum voltage level for the memory device. ### Claim 19 (depends on 18) The method of claim 18, wherein adjusting the output voltage further comprises computing the tolerance amount based on a reactive component of the power profile for the memory device. ### Claim 20 (depends on 16) The method of claim 16, wherein adjusting the output voltage level further comprises digitally controlling the voltage level. ### Claim 21 (depends on 20) The method of claim 20, wherein digitally controlling the voltage level further comprises generating a digital signal to control a digital to analog converter to adjust the output voltage.