# US 2014/0192606 A1 · Stacked memory device, memory system including the same and method for operating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0192606 A1 - Document ID: US20140192606A1 - Status: Published application - Kind: A1 - Application number: 14/103,090 - Filed: 2013-12-11 - Published: 2014-07-10 - Earliest claimed: 2013-01-08 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Gil Young KANG; Chi Sung OH - Web page: https://patentgrep.com/patent/US20140192606A1 ## CPC - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 11/40611: {External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A stacked memory device includes a plurality of interconnected memory chips and a controller to control the plurality of memory chips to perform refresh operations during non-overlapping time periods. Each memory chip includes a plurality of ranks, and each rank includes at least one memory bank. In one arrangement, the controller controls the refresh operation to be selectively performed for a first rank in each of the memory chips during the non-overlapping time periods independently from a refresh operation performed for a second rank in each memory chip. Delay circuits or other logic may be included to ensure that the refresh operations do not overlap. ## Claims ### Claim 1 A stacked memory device, comprising: a plurality of memory chips; a first path to transmit a command signal to at least one of the plurality of memory chips; and a second path coupled to the plurality of memory chips, the second path to transmit a refresh control signal for controlling a refresh operation of at least one of the plurality of memory chips. ### Claim 2 (depends on 1) The stacked memory device as claimed in claim 1, further comprising: a memory controller to control the plurality of memory chips, and wherein the memory controller includes a generator to generate the refresh control signal. ### Claim 3 (depends on 1) The stacked memory device as claimed in claim 1, wherein at least one of the plurality of memory chips includes a refresh control circuit to control the refresh operation based on the refresh control signal. ### Claim 4 (depends on 3) The stacked memory device as claimed in claim 3, wherein the refresh control circuit includes a generator to generate the refresh control signal. ### Claim 5 (depends on 3) The stacked memory device as claimed in claim 3, wherein the refresh control circuit includes a refresh control block to count time in response to the refresh control signal and to output the refresh control signal based on the counted value. ### Claim 6 (depends on 3) The stacked memory device as claimed in claim 3, wherein the refresh control circuit includes a delay circuit to delay the refresh control signal. ### Claim 7 (depends on 1) The stacked memory device as claimed in claim 1, wherein the refresh control signal is a power oscillator signal. ### Claim 8 (depends on 1) The stacked memory device as claimed in claim 1, wherein the refresh operation is a self-refresh operation. ### Claim 9 (depends on 1) The stacked memory device as claimed in claim 1, wherein at least one of the plurality of memory chips includes a vertical electrical connection structure. ### Claim 10 (depends on 1) A memory system comprising: the stacked memory device as claimed in claim 1; and a system-on-chip including a memory controller to control the stacked memory device. ### Claim 11 A method for operating a stacked memory device including a plurality of memory chips, the method comprising: generating a refresh control signal; and performing a refresh operation of at least one of the plurality of memory chips according to the refresh control signal. ### Claim 12 (depends on 11) The method as claimed in claim 11, wherein each of the plurality of memory chips receives the refresh control signal through a same path. ### Claim 13 (depends on 11) The method as claimed in claim 11, wherein performing the refresh operation comprises: delaying the refresh control signal; and performing the refresh operation of at least one of the plurality of memory chips in response to the delayed refresh control signal. ### Claim 14 (depends on 11) The method as claimed in claim 11, wherein performing the refresh operation comprises: counting a time in response to the refresh control signal; and performing the refresh operation of at least one of the plurality of memory chips according to the counted time. ### Claim 15 (depends on 11) The method as claimed in claim 11, wherein performing the refresh operation includes: performing a refresh operation for each of the plurality of memory chips according to the refresh control signal, wherein each of the plurality of memory chips performs a refresh operation at a time different from the refresh operation performed by remaining ones of the plurality of memory chips. ### Claim 16 A stacked memory device, comprising: a plurality of memory chips; and a controller to control the plurality of memory chips, wherein the controller controls the memory chips to independently perform refresh operations during non-overlapping time periods. ### Claim 17 (depends on 16) The stacked memory device of claim 16, wherein: each memory chip includes a plurality of ranks, each rank includes at least one memory bank, and the controller controls the refresh operation to be selectively performed for a first rank in each of the memory chips during the non-overlapping time periods independently from a refresh operation performed for a second rank in each memory chip. ### Claim 18 (depends on 17) The stacked memory device of claim 17, wherein the first rank in each of the memory chips is included in a same channel. ### Claim 19 (depends on 18) The stacked memory device of claim 18, further comprising: a connection structure to connect the first rank in each of the memory chips, the connection structure to send a refresh control signal from the controller to a refresh control circuit in each of the memory chips. ### Claim 20 (depends on 19) The stacked memory device of claim 19, wherein the refresh control signal is a power oscillation signal.