# US 2014/0192605 A1 · Memory refresh management

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- Number: US 2014/0192605 A1
- Document ID: US20140192605A1
- Status: Published application
- Kind: A1
- Application number: 13/761,385
- Filed: 2013-02-07
- Published: 2014-07-10
- Earliest claimed: 2013-01-04
- Assignees: Intel Corporation
- Inventors: John H. Crawford; Suneeta Sah
- Web page: https://patentgrep.com/patent/US20140192605A1

## CPC

- G06F 3/0613: {in relation to throughput}
- G06F 3/0658: {Controller construction arrangements}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0673: {Single storage device}
- G11C 11/40611: {External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh}
- G11C 11/40618: {Refresh operations over multiple banks or interleaving}
- G11C 11/406: Management or control of the refreshing or charge-regeneration cycles
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Apparatus, systems, and methods to manage memory refresh operations are described. In one embodiment, an electronic device comprises a processor and memory controller logic to determine a memory refresh frequency for a memory system and transmit refresh commands to a refresh control logic in at least one memory bank coupled to the memory controller according to the memory refresh frequency. Other embodiments are also disclosed and claimed.

## Claims

### Claim 1

An electronic device comprising:
a processor; and
a memory control logic to:
determine a memory refresh frequency for a memory system; and
transmit refresh commands to a refresh control logic in at least one memory bank coupled to the memory controller according to the memory refresh frequency.

### Claim 2 (depends on 1)

The electronic device of claim 1, further comprising logic to:
retrieve a memory refresh parameter from a register in the at least one memory bank; and
use the memory refresh parameter to determine the memory refresh frequency.

### Claim 3 (depends on 2)

The electronic device of claim 2, further comprising logic to:
retrieve a plurality of memory refresh parameters from a plurality of memory banks coupled to the memory controller;
determine a maximum memory refresh parameter; and
set the memory refresh frequency to the maximum refresh parameter.

### Claim 4 (depends on 3)

The electronic device of claim 3, wherein the memory controller comprises logic to generate refresh commands at a first refresh frequency which is constant.

### Claim 5 (depends on 3)

The electronic device of claim 3, wherein the memory controller comprises logic to generate additional refresh commands at a second refresh frequency which is different than the first refresh frequency.

### Claim 6 (depends on 3)

The electronic device of claim 3, wherein the memory controller comprises logic to generate refresh commands at a refresh frequency which varies over time in response to changes in the memory system.

### Claim 7 (depends on 1)

The electronic device of claim 1 wherein refresh control logic in the memory bank comprises logic to:
determine a refresh requirement for one or more rows in the memory bank; and
store the refresh requirement in a memory register in association with a row address.

### Claim 8 (depends on 7)

The electronic device of claim 7 wherein refresh control logic in the memory bank comprises logic to:
receive a refresh command from the memory controller;
select a row from the memory register; and
implement a refresh operation on the row.

### Claim 9 (depends on 7)

The electronic device of claim 7, wherein refresh control logic in the memory bank comprises logic to reorder refresh operations in the memory bank according to refresh requirements of rows of memory in the memory bank.

### Claim 10 (depends on 1)

The electronic device of claim 1, wherein the memory controller further comprises logic to:
identify one or more rows in the at least one memory bank which require more frequent refresh operations; and
update a refresh frequency parameter for this one or more rows.

### Claim 11

A memory controller comprising logic to:
determine a memory refresh frequency for a memory system; and
transmit refresh commands to a refresh control logic in at least one memory bank coupled to the memory controller according to the memory refresh frequency.

### Claim 12 (depends on 11)

The memory controller of claim 11, further comprising logic to:
retrieve a memory refresh parameter from a register in the at least one memory bank; and
use the memory refresh parameter to determine the memory refresh frequency.

### Claim 13 (depends on 12)

The memory controller of claim 12, further comprising logic to:
retrieve a plurality of memory refresh parameters from a plurality of memory banks coupled to the memory controller;
determine a maximum memory refresh parameter; and
set the memory refresh frequency to the maximum refresh parameter.

### Claim 14 (depends on 13)

The memory controller of claim 13, wherein the memory controller comprises logic to generate refresh commands at a first refresh frequency which is constant.

### Claim 15 (depends on 13)

The memory controller of claim 13, wherein the memory controller comprises logic to generate additional refresh commands at a second refresh frequency which is different than the first refresh frequency.

### Claim 16 (depends on 13)

The memory controller of claim 13, wherein the memory controller comprises logic to generate refresh commands at a refresh frequency which varies over time in response to changes in the memory system.

### Claim 17 (depends on 13)

The memory controller of claim 13, wherein the memory controller further comprises logic to:
identify one or more rows in the at least one memory bank which require more frequent refresh operations; and
update a refresh frequency parameter for this one or more rows.

### Claim 18

An apparatus comprising:
a memory device having a plurality of memory cells organized into rows;
a memory register; and
a memory refresh control logic to:
determine a refresh requirement for one or more rows in the memory device; and
store the refresh requirement in a memory register in association with a row address.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the memory refresh control logic in the memory device comprises logic to:
receive a refresh command from a memory controller;
select a row from the memory register; and
implement a refresh operation on the row.

### Claim 20 (depends on 18)

The apparatus of claim 18, wherein refresh control logic in the memory device comprises logic to reorder refresh operations in the memory bank according to refresh requirements of rows of memory in the memory bank.

### Claim 21

A method comprising:
determining, in a memory controller, a memory refresh frequency for a memory system; and
transmitting refresh commands to a refresh control logic in at least one memory bank coupled to the memory controller according to the memory refresh frequency.

### Claim 22 (depends on 21)

The method of claim 21, further comprising:
retrieving a memory refresh parameter from a register in the at least one memory bank; and
using the memory refresh parameter to determine the memory refresh frequency.

### Claim 23 (depends on 22)

The method of claim 22, further comprising:
retrieving a plurality of memory refresh parameters from a plurality of memory banks coupled to the memory controller;
determining a maximum memory refresh parameter; and
setting the memory refresh frequency to the maximum refresh parameter.

### Claim 24 (depends on 23)

The method of claim 23, further comprising generating refresh commands at a first refresh frequency which is constant.

### Claim 25 (depends on 23)

The method of claim 23, further comprising generating additional refresh commands at a second refresh frequency which is different than the first refresh frequency.