# US 2014/0192604 A1 · Memory cell operation

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- Number: US 2014/0192604 A1
- Document ID: US20140192604A1
- Status: Published application
- Kind: A1
- Application number: 14/171,243
- Filed: 2014-02-03
- Published: 2014-07-10
- Earliest claimed: 2011-05-27
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Roy E. Meade; John K. Zahurak
- Web page: https://patentgrep.com/patent/US20140192604A1

## CPC

- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0011: {comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]}
- G11C 13/0038: {Power supply circuits}
- G11C 13/0061: {Timing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Methods, devices, and systems associated with memory cell operation are described. One or more methods of operating a memory cell include charging a capacitor coupled to the memory cell to a particular voltage level and programming the memory cell from a first state to a second state by controlling discharge of the capacitor through a resistive switching element of the memory cell.

## Claims

### Claim at position 1

1-19. (canceled)

### Claim 20

A method for operating a memory cell, comprising:
charging a capacitor coupled to the memory cell to a particular voltage level; and
discharging the capacitor through the memory cell to program the memory cell, wherein the discharge of the capacitor provides a magnitude of current sufficient to program the memory cell from a first state to a second state and the capacitor is a stray capacitance that includes a conductive line parasitic capacitance.

### Claim 21 (depends on 20)

The method of claim 20, wherein the conductive line parasitic capacitance includes a capacitance between a first access line and a second access line.

### Claim 22 (depends on 21)

The method of claim 21, wherein the first access line and the second access line are each word lines.

### Claim 23 (depends on 22)

The method of claim 22, wherein the first access line is selected for programming the memory cell and the second access line is unselected for programming the memory cell.

### Claim 24 (depends on 23)

The method of claim 23, wherein the first access line is tied to a ground relative the second access line.

### Claim 25 (depends on 20)

The method of claim 20, wherein the conductive line parasitic capacitance includes a capacitance between an access line and a data/sense line.

### Claim 26 (depends on 25)

The method of claim 25, wherein the access line is a word line and the data/sense line is a bit line.

### Claim 27 (depends on 26)

The method of claim 26, wherein the access line is selected for programming the memory cell.

### Claim 28

A memory device, comprising:
an array of memory cells;
control circuitry coupled to the array to charge a capacitor coupled to a selected memory cell to a particular voltage level and provide a magnitude of current, by discharge of the capacitor, to the selected memory cell sufficient to program the selected memory cell from a first state to a second state; and
a switch located between a voltage source and the selected memory cell, wherein opening the switch adjusts a bias applied to an access line corresponding to the selected memory cell.

### Claim 29 (depends on 28)

The memory device of claim 28, wherein the array of memory cells includes a plurality of single level memory cells.

### Claim 30 (depends on 28)

The memory device of claim 28, wherein the array of memory cells includes a plurality of multiple level memory cells.

### Claim 31 (depends on 28)

The memory device of claim 28, wherein the capacitor has a capacitance of about 100 femtofarads to about 300 femtofarads.

### Claim 32 (depends on 28)

The memory device of claim 28, wherein, including a select device coupled to a storage element of the selected memory cell.

### Claim 33 (depends on 28)

The memory device of claim 28, wherein the array of memory cells includes a plurality of conductive bridging cells.

### Claim 34 (depends on 29)

The memory device of claim 29, wherein the array of memory cells includes a plurality of programmable metallization cells.

### Claim 35

A method of operating a memory cell, comprising:
closing a switch that is coupled to the memory cell to apply a bias to an access line coupled to the memory cell to charge an access line parasitic capacitor;
opening the switch to adjust the bias;
discharging the access line parasitic capacitor through the memory cell, wherein the discharge provides a magnitude of current sufficient to program the memory cell from a first state to a second state; and
charging a bit line parasitic capacitor via the discharge of the access line parasitic capacitor.

### Claim 36 (depends on 36)

The method of claim 36, including providing a potential difference across the memory cell by adjusting a bit line bias.

### Claim 37 (depends on 36)

The method of claim 36, wherein adjusting a bit line bias includes reducing the bit line bias.

### Claim 38 (depends on 35)

The method of claim 35, including shielding the memory cell from prematurely programming from the first state to the second state by biasing a bit line.

### Claim 39 (depends on 35)

The method of claim 35, wherein opening the switch to adjust the bias includes removing a voltage from the access line.