# US 2014/0192602 A1 · Defective memory column replacement with load isolation

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- Number: US 2014/0192602 A1
- Document ID: US20140192602A1
- Status: Published application
- Kind: A1
- Application number: 13/733,948
- Filed: 2013-01-04
- Published: 2014-07-10
- Earliest claimed: 2013-01-04
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Silke Penth; Raphael Polig; Tobias Werner; Alexander Woerner
- Web page: https://patentgrep.com/patent/US20140192602A1

## CPC

- G11C 29/04: Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals}
- G11C 29/785: {with redundancy programming schemes}
- G11C 29/832: {with disconnection of faulty elements}
- G11C 11/41: forming {static} cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Exemplary embodiments of the present invention disclose a method and system for substituting a group of memory cells for a defective group of memory cells in a memory. In a step, an exemplary embodiment replaces a signal path to a group of defective memory cells with a signal path to a redundant group of memory cells. In another step, an exemplary embodiment isolates the signal path to the redundant group of memory cells from a load imposed by the signal path to the replaced group of defective memory cells.

## Claims

### Claim 1

A system for substituting a group of memory cells in a memory, the system comprising:
one or more groups of memory cells;
one or more redundant groups of memory cells;
circuit to replace a signal path to a defective group of memory cells with a signal path to a redundant group of memory cells;
circuit to isolate the signal path to the redundant group of memory cells from a load imposed by the signal path to the defective group of memory cells that has been replaced;
wherein the system is operable to:
replace a signal path to a group of defective memory cells with a signal path to a redundant group of memory cells; and
isolate the signal path to the redundant group of memory cells from a load imposed by the replaced signal path to the group of defective memory cells.

### Claim 2 (depends on 1)

The system of claim 1, wherein the memory is a semiconductor memory.

### Claim 3 (depends on 2)

The system of claim 2, wherein the semiconductor memory is an SRAM.

### Claim 4 (depends on 2)

The system of claim 2, wherein the semiconductor memory is a DRAM.

### Claim 5 (depends on 1)

The system of claim 1, wherein the signal paths are input signal paths.

### Claim 6 (depends on 5)

The system of claim 5, wherein the memory is a semiconductor memory.

### Claim 7 (depends on 6)

The system of claim 6, wherein the semiconductor memory is an SRAM.

### Claim 8 (depends on 6)

The system of claim 6, wherein the semiconductor memory is a DRAM.

### Claim 9 (depends on 5)

The system of claim 5, wherein the input signal paths are input bit signal paths.

### Claim 10 (depends on 9)

The system of claim 9, wherein the memory is a semiconductor memory.

### Claim 11 (depends on 10)

The system of claim 10, wherein the semiconductor memory is an SRAM.

### Claim 12 (depends on 10)

The system of claim 10, wherein the semiconductor memory is a DRAM.

### Claim 13

A method for substituting a group of memory cells in a memory, the method comprising the steps of:
replacing a signal path to a group of defective memory cells with a signal path to a redundant group of memory cells; and
isolating the signal path to the redundant group of memory cells from a load imposed by the replaced signal path to the group of defective memory cells.

### Claim 14 (depends on 13)

The method of claim 13, wherein the memory cells in the replacing and isolating steps are semiconductor memory.

### Claim 15 (depends on 14)

The method of claim 14, wherein the semiconductor memory cells in the replacing and isolating steps are SRAM.

### Claim 16 (depends on 14)

The method of claim 14, wherein the semiconductor memory cells in the replacing and isolating steps are DRAM.

### Claim 17 (depends on 13)

The method of claim 13, wherein the signal paths in the replacing and isolating steps are input signal paths.

### Claim 18 (depends on 17)

The method of claim 17, wherein the memory cells in the replacing and isolating steps are semiconductor memory.

### Claim 19 (depends on 18)

The method of claim 18, wherein the semiconductor memory cells in the replacing and isolating steps are SRAM.

### Claim 20 (depends on 18)

The method of claim 18, wherein the semiconductor memory cells in the replacing and isolating steps are DRAM.