# US 2014/0192600 A1 · Eeprom cell and eeprom device

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- Number: US 2014/0192600 A1
- Document ID: US20140192600A1
- Status: Published application
- Kind: A1
- Application number: 13/963,330
- Filed: 2013-08-09
- Published: 2014-07-10
- Earliest claimed: 2013-01-04
- Assignees: Electronics and Telecommunications Research Institute
- Applicants: Electronics and Telecommunications Research Institute
- Inventors: Jin-Yeong KANG
- Web page: https://patentgrep.com/patent/US20140192600A1

## CPC

- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/045: {Floating gate memory cells with both P and N channel memory transistors, usually sharing a common floating gate}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An EEPROM cell is provided which includes a control gate; a tunneling plate; a floating plate configured to form a capacitor area with the control plate and the tunneling plate; an inverter configured to sense a voltage level of the floating plate; a first transfer gate connected with the tunneling plate and configured to transfer an operating voltage selectively applied from first and second bit lines to the tunneling plate; a protection circuit connected with the inverter and configured to float the inverter at non-read or write/erase operations of an adjacent EEPROM cell; and a second transfer gate configured to transfer an output voltage of the inverter. This configuration is enable to use all the same gate oxide (i.e. 26 Å) and ultra low operation voltages (i.e. ±2V) in EEPROM cell.

## Claims

### Claim 1

An EEPROM cell, comprising:
a control gate;
a tunneling plate;
a floating plate configured to form a capacitor area with the control plate and the tunneling plate;
an inverter configured to sense a voltage level of the floating plate;
a first transfer gate connected with the tunneling plate and configured to transfer an operating voltage selectively applied from first and second bit lines to the tunneling plate;
a protection circuit connected with sources of the floated inverter at write and erase operations of an adjacent EEPROM cell; and
a second transfer gate configured to transfer an output voltage of the inverter.

### Claim 2 (depends on 1)

The EEPROM cell of claim 1, wherein the protection circuit comprises:
a PMOS transistor configured to supply a power supply voltage to the inverter in response to an externally applied read voltage; and
an NMOS transistors configured to supply a ground voltage to the inverter in response to the externally applied read voltage.

### Claim 3 (depends on 2)

The EEPROM cell of claim 2, wherein the PMOS transistor has a gate grounded, a source connected with a read voltage line supplied with the externally applied read voltage, and a drain connected with the inverter and the NMOS transistor has a gate connected with the read voltage line, a source grounded, and a drain connected with the drain of the inverter.

### Claim 4 (depends on 3)

The EEPROM cell of claim 3, wherein the PMOS transistor transfers a power supply voltage to the inverter in response to the read voltage at a sensing operation and the NMOS transistor transfer a ground voltage to the inverter in response to the read voltage at the sensing operation.

### Claim 5 (depends on 4)

The EEPROM cell of claim 4, wherein at remaining operations excluding the sensing operation, the read voltage has a ground voltage level and a source and a drain of the inverter are floated.

### Claim 6 (depends on 1)

The EEPROM cell of claim 1, wherein the first transfer gate comprises:
a PMOS transistor configured to transfer a voltage of the first bit line to the tunneling plate; and
an NMOS transistor configured to transfer a voltage of the second bit line to the tunneling plate.

### Claim 7 (depends on 6)

The EEPROM cell of claim 6, wherein a positive voltage is applied to the first bit line and a negative voltage is applied to the second bit line.

### Claim 8 (depends on 7)

The EEPROM cell of claim 7, wherein when a voltage is applied to one of the first and second bit lines, the other is floated.

### Claim 9 (depends on 8)

The EEPROM cell of claim 8, wherein the PMOS transistor has a gate grounded, a source connected with the first bit line, and a drain connected with the tunneling plate and the NMOS transistor has a gate grounded, a source connected with the second bit line, and a drain connected with the tunneling plate.

### Claim 10 (depends on 9)

The EEPROM cell of claim 9, wherein outputs of the PMOS and NMOS transistors are prevented from back flow of a signal even though connected to common tunneling plate line.

### Claim 11 (depends on 1)

The EEPROM cell of claim 1, wherein the second transfer gate is connected with a first sense gate line and a second sense gate line and transfers an output voltage of the inverter to a sense line.

### Claim 12 (depends on 11)

The EEPROM cell of claim 11, wherein the second transfer gate comprises:
the gate of PMOS transistor connected with the first sense gate line; and
the gate of NMOS transistor connected with the second sense gate line,
wherein at a sensing operation, a ground voltage is applied to the gate of PMOS transistor through the first sense gate line and a power supply voltage is applied to the gate of NMOS transistor through the second sense gate line.

### Claim 13 (depends on 12)

The EEPROM cell of claim 12, wherein the PMOS transistor has a drain connected with the inverter, a source connected with the sense line, and a gate connected with the first sense gate line and the NMOS transistor has a source connected with the inverter, a drain connected with the sense line, and a gate connected with the second sense gate line.

### Claim 14 (depends on 11)

The EEPROM cell of claim 11, wherein insulation films in elements constituting the inverter, the first and second transfer gates and the protection circuit have the same thickness.

### Claim 15 (depends on 14)

The EEPROM cell of claim 14, wherein the insulation film is an gate oxide film and is formed to have a thickness less than about 70 angstroms.

### Claim 16

An EEPROM device, comprising:
an EEPROM cell array including EEPROM cells arranged in a matrix of rows and columns, each EEPROM cell having an inverter and a transfer gate,
wherein each of the EEPROM cell further includes a protection circuit enabling a tunneling oxide film to be formed with the same thickness as insulation films of the inverter and the transfer gate.

### Claim 17 (depends on 16)

The EEPROM device of claim 16, wherein each of the EEPROM cell comprises:
a control gate;
a tunneling plate; and
a floating plate configured to form a capacitor area with the control plate and the tunneling plate, the inverter configured to sense a voltage level of the floating plate,

### Claim 18 (depends on 17)

The EEPROM device of claim 17, wherein the protection circuit is connected with a corresponding inverter and floats the corresponding inverter when a corresponding EEPROM cell is not selected.

### Claim 19 (depends on 18)

The EEPROM device of claim 18, wherein the protection circuit supplies a voltage of a drain and a source of an inverter only at a read mode and comprises:
a PMOS transistor configured to supply a power supply voltage to the inverter in response to an externally applied read voltage; and
an NMOS transistor configured to supply a ground voltage to the inverter in response to the externally applied read voltage.

### Claim 20 (depends on 19)

The EEPROM device of claim 19, wherein the PMOS transistor has a gate grounded, a source connected with a read voltage line supplied with the externally applied read voltage, and a drain connected with the inverter and the NMOS transistor has a gate connected with the read voltage line, a source grounded, and a drain connected with the inverter, the read voltage having a ground voltage level at remaining operations excluding the sensing operation.