# US 2014/0192597 A1 · Circuit for controlling eeprom cell > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0192597 A1 - Document ID: US20140192597A1 - Status: Published application - Kind: A1 - Application number: 13/911,310 - Filed: 2013-06-06 - Published: 2014-07-10 - Earliest claimed: 2013-01-04 - Assignees: Electronics and Telecommunications Research Institute - Applicants: Electronics and Telecommunications Research Institute - Inventors: Jin-Yeong KANG - Web page: https://patentgrep.com/patent/US20140192597A1 ## CPC - G11C 16/24: Bit-line control circuits - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract An EEPROM cell control circuit is provided which includes a signal input circuit configured to receive control signals for controlling an EEPROM cell from an external device; a bit line control circuit configured to provide a positive voltage and a negative voltage to two bit lines connected with the EEPROM cell in response to the control signals; and a word line control circuit configured to control a sense gate line in response to the control signals at a sense operation and to apply a positive voltage and a negative voltage to a word line. ## Claims ### Claim 1 An EEPROM cell control circuit, comprising: a signal input circuit configured to receive control signals for controlling an EEPROM cell from an external device; a bit line control circuit configured to provide a positive voltage and a negative voltage to two bit lines connected with the EEPROM cell in response to the control signals; and a word line control circuit configured to control a sense gate line in response to the control signals at a sense operation and to apply a positive voltage and a negative voltage to a word line. ### Claim 2 (depends on 1) The EEPROM cell control circuit of claim 1, wherein the input circuit comprises: a first inverter configured to select either program and erase operations or standby and read operations; a second inverter configured to receive a program/erase mode control signal for controlling a program mode and an erase mode; and a third inverter configured to receive a word line selection signal for word line selection. ### Claim 3 (depends on 1) The EEPROM cell control circuit of claim 1, wherein the bit line control circuit comprises: a first AND gate configured to receive control signals for applying a negative voltage to a first bit line of the two bit lines; a first voltage level converter connected with the first AND gate and to apply a negative voltage to the first bit line; a first NAND gate configured to receive control signals for applying a positive voltage to a second bit line of the two bit lines; and a second voltage level converter connected with the first NAND gate and to apply a positive voltage to the second bit line. ### Claim 4 (depends on 3) The EEPROM cell control circuit of claim 3, wherein each of the first and second voltage level converters comprises: an input unit configured to receive a signal; voltage level conversion units connected to have a three-stage structure and to convert a voltage of the input signal based on a power supply voltage, a ground voltage, a high output voltage, a low output voltage, and an intermediate voltage; an output unit configured to output a signal the voltage of which is converted by the voltage level conversion units; and an operating voltage stabilizer configured to secure a normal function operation although a difference between operating voltages of elements in a voltage level conversion unit, located at a first stage, from among the voltage level conversion units is generated and to suppress power consumption. ### Claim 5 (depends on 4) The EEPROM cell control circuit of claim 4, wherein the operating voltage stabilizer includes two NMOS transistors connected with the intermediate voltage. ### Claim 6 (depends on 1) The EEPROM cell control circuit of claim 1, wherein the word line control circuit comprises: a second NAND gate configured to receive a word line selection signal and a control signal for applying different voltages to two sense gate lines of the EEPROM cell at a read operation; and a first inverter circuit connected with the second NAND gate and configured to apply an operating voltage for the read operation to the two sense gate lines of the EEPROM cell. ### Claim 7 (depends on 1) The EEPROM cell control circuit of claim 1, wherein the word line control circuit comprises: a second inverter circuit configured to receive a word line selection signal and a control signal for generating a voltage applied to a read voltage line at a read operation and to apply a read voltage to the read voltage line. ### Claim 8 (depends on 1) The EEPROM cell control circuit of claim 1, further comprising: a CMOS logic circuit configured to receive a word line selection signal and a control signal for generation of a positive voltage and a negative voltage applied to the word line; a third voltage level converter connected with the CMOS logic circuit and to generate a positive voltage applied to the word line; a first transfer gate configured to transfer an output of the third voltage level converter to the word line; a fourth voltage level converter connected with the CMOS logic circuit and to generate a negative voltage applied to the word line; and a second transfer gate configured to transfer an output of the fourth voltage level converter to the word line. ### Claim 9 (depends on 8) The EEPROM cell control circuit of claim 8, wherein a bias condition between drains and wells of the first and second transfer gates are at a reverse bias state such that a signal is not transferred between the first and second transfer gates. ### Claim 10 (depends on 9) The EEPROM cell control circuit of claim 9, wherein the first transfer gate generates a positive voltage, a zero voltage, and high-impedance, and the second transfer gate generates a negative voltage and high-impedance. ### Claim 11 (depends on 8) The EEPROM cell control circuit of claim 8, wherein the CMOS logic circuit comprises: second and third NAND gates configured to receive a word line selection signal and a control signal for generation of a positive voltage of the third voltage level converter; a first NOR gate configured to perform a NOR operation on outputs of the second and third NAND gates to output a result of the NOR operation to the third voltage level converter; fourth and fifth NAND gates configured to receive a word line selection signal and a control signal for generation of a negative voltage of the fourth voltage level converter; and a second NOR gate configured to perform a NOR operation on outputs of the fourth and fifth NAND gates to output a result of the NOR operation to the fourth voltage level converter. ### Claim 12 (depends on 8) The EEPROM cell control circuit of claim 8, wherein each of the third and fourth voltage level converters comprises: an input unit configured to receive a signal; voltage level conversion units connected to have a three-stage structure and to convert a voltage of the input signal based on a power supply voltage, a ground voltage, a high output voltage, a low output voltage, and an intermediate voltage; an output unit configured to output a signal the voltage of which is converted by the voltage level conversion units; and an operating voltage stabilizer configured to secure a normal function operation although a difference between operating voltages of elements in a voltage level conversion unit, located at a first stage, from among the voltage level conversion units is generated and to suppress power consumption. ### Claim 13 (depends on 12) The EEPROM cell control circuit of claim 12, wherein the operating voltage stabilizer includes two NMOS transistors connected with the intermediate voltage.