# US 2014/0192596 A1 · Nonvolatile memory with split substrate select gates and heirarchical bitline configuration

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- Number: US 2014/0192596 A1
- Document ID: US20140192596A1
- Status: Published application
- Kind: A1
- Application number: 13/830,054
- Filed: 2013-03-14
- Published: 2014-07-10
- Earliest claimed: 2013-01-10
- Assignees: Mosaid Technologies Incorporated
- Applicants: Mosaid Technologies Incorporated
- Inventors: Hyoung Seub RHIE
- Web page: https://patentgrep.com/patent/US20140192596A1

## CPC

- G11C 11/5635: {Erasing circuits}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Generally, the present disclosure provides a non-volatile memory device having a hierarchical bitline structure for preventing erase voltages applied to one group of memory cells of the memory array from leaking to other groups in which erasure is not required. Local bitlines are coupled to the memory cells of each group of memory cells. Each local bitline can be selectively connected to a global bitline during read operations for the selected group, and all the local bitlines can be disconnected from the global bitline during an erase operation when a specific group is selected for erasure. Select devices for electrically connecting each bitline of a specific group of memory cells to the global bitline have device bodies that are electrically isolated from the bodies of those memory cells.

## Claims

### Claim 1

A non-volatile memory comprising:
at least two groups of non-volatile memory cells each eraseable in an erase operation;
local bitlines coupled to the non-volatile memory cells of each group of the at least two groups;
a global bitline; and
a select device corresponding to each of the at least two groups configured to disconnect all the local bitlines from the global bitline.

### Claim 2 (depends on 1)

The non-volatile memory of claim 1, wherein a body of the select device for electrically connecting a local bitline coupled to the non-volatile memory cells of one group of the at least two groups to the global bitline, is electrically isolated from bodies of the non-volatile memory cells of the one group.

### Claim 3 (depends on 2)

The non-volatile memory of claim 2, wherein the non-volatile memory cells are arranged as NAND cell strings.

### Claim 4 (depends on 3)

The non-volatile memory of claim 3, wherein each of the at least two groups of non-volatile memory cells are formed in corresponding pocket wells of a substrate and are electrically isolated from each other.

### Claim 5 (depends on 4)

The non-volatile memory of claim 4, wherein each of the corresponding pocket wells is connected to a local erase line for receiving an erase voltage.

### Claim 6 (depends on 5)

The non-volatile memory of claim 5, wherein the select device is formed in a region of the substrate external to the pocket wells.

### Claim 7 (depends on 6)

The non-volatile memory of claim 6, wherein the pocket wells have a first dopant type and are formed in a well having a second dopant type, the well being formed in the substrate having the first dopant type.

### Claim 8 (depends on 7)

The non-volatile memory of claim 7, wherein the first dopant type is p-type and the second dopant type is n-type.

### Claim 9 (depends on 6)

The non-volatile memory of claim 6, wherein the NAND cell strings comprise planar NAND cell strings.

### Claim 10 (depends on 6)

The non-volatile memory of claim 6, wherein the NAND cell strings comprise three-dimension (3D) stacked NAND cell strings having a body with a vertical channel electrically coupled to a respective pocket well.

### Claim 11 (depends on 6)

The non-volatile memory of claim 6, wherein a first select device corresponding to a first group of the at least two groups and a second select device corresponding to a second group of the at least two groups are formed adjacent to each other in the substrate and share a single contact to the global bit line.

### Claim 12 (depends on 3)

The non-volatile memory of claim 3, wherein the NAND cell strings comprise 3D stacked NAND cell strings having bodies electrically isolated from a substrate.

### Claim 13 (depends on 12)

The non-volatile memory of claim 12, wherein the select device corresponding to each of the at least two groups are formed in the substrate.

### Claim 14 (depends on 13)

The non-volatile memory of claim 13, wherein a source line is formed in the substrate and electrically isolates the bodies from the substrate.

### Claim 15 (depends on 14)

The non-volatile memory of claim 14, wherein the bodies have a first dopant type, the source line has a second dopant type, and the substrate has the first dopant type.

### Claim 16 (depends on 15)

The non-volatile memory of claim 15, wherein the first dopant type is p-type and the second dopant type is n-type.

### Claim 17 (depends on 13)

The non-volatile memory of claim 13, wherein the source line is formed as a conductive line over the substrate.

### Claim 18 (depends on 13)

The non-volatile memory of claim 13, wherein a first select device corresponding to a first group of the at least two groups and a second select device corresponding to a second group of the at least two groups are formed adjacent to each other in the substrate and share a single contact to the global bit line.

### Claim 19 (depends on 3)

The non-volatile memory of claim 3, wherein each of the at least two groups includes at least two NAND memory blocks of NAND cell strings.

### Claim 20 (depends on 1)

The non-volatile memory of claim 1, wherein the select device corresponding to each of the at least two groups includes a pass transistor enabled by a local bitline select signal.

### Claim 21 (depends on 20)

The non-volatile memory of claim 20, further including row decoding circuitry configured to provide the local bitline select signal corresponding to each pass transistor for disconnecting all the local bitlines from the global bitline in an erase operation.