# US 2014/0192595 A1 · Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines and a Single-Sided Word Line Architecture

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- Number: US 2014/0192595 A1
- Document ID: US20140192595A1
- Status: Published application
- Kind: A1
- Application number: 14/153,794
- Filed: 2014-01-13
- Published: 2014-07-10
- Earliest claimed: 2009-04-08
- Assignees: SanDisk 3D LLC
- Applicants: SanDisk 3D LLC
- Inventors: George Samachisa
- Web page: https://patentgrep.com/patent/US20140192595A1

## CPC

- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- G11C 11/06035: {Bit core selection for writing or reading, by at least two coincident partial currents, e.g. "bit"- organised, 2L/2D, or 3D}
- G11C 11/5614: {using conductive bridging RAM [CBRAM] or programming metallization cells [PMC]}
- G11C 11/5678: {using amorphous/crystalline phase transition storage elements}
- G11C 11/5685: {using storage elements comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0011: {comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]}
- G11C 13/003: {Cell access}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0064: {Verifying circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 13/025: {using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes}
- G11C 16/10: Programming or data input circuits
- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- H10B 63/845: {the switching components being connected to a common vertical conductor}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/841: {Electrodes}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10W 20/43: Layouts of interconnections
- G11C 2013/0045: {Read using current through the cell}
- G11C 2013/0088: {Write with the simultaneous writing of a plurality of cells}
- G11C 2213/19: Memory cell comprising at least a nanowire and only two terminals
- G11C 2213/32: Material having simple binary metal oxide structure
- G11C 2213/34: Material includes an oxide or a nitride
- G11C 2213/55: Structure including two electrodes, a memory active layer and at least two other layers which can be a passive or source or reservoir layer or a less doped memory active layer
- G11C 2213/71: Three dimensional array
- G11C 2213/75: Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
- G11C 2213/78: Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver
- H10N 70/235: {between different crystalline phases, e.g. cubic and hexagonal}
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/245: {the species being metal cations, e.g. programmable metallization cells}
- H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices}
- H10N 70/8416: {adapted for supplying ionic species}
- H10N 70/8822: {Sulfides, e.g. CuS}
- H10N 70/8825: {Selenides, e.g. GeSe}
- H10N 70/884: {based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors (compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883)}
- H10N 70/8845: {Carbon or carbides}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.

## Claims

### Claim 1

A data memory including memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having orthogonal x, y and z-directions and with a plurality of parallel planes stacked in the z-direction, the memory further comprising:
a plurality of first conductive lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array in the x and y-directions,
a plurality of second conductive lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the first plurality of conductive lines in the individual planes, wherein the first and second conductive lines cross adjacent each other at a plurality of locations across the individual planes,
a plurality of non-volatile re-programmable memory elements individually connected between the first and second conductive lines adjacent the crossings thereof at the plurality of locations, and
a plurality of select devices arranged to individually connect selected ones of the plurality of first conductive lines to selected ones of a plurality of third conductive lines; and
wherein the memory elements are sandwiched in the y-direction between the first and second conductive lines and are provided in continuous sheets of non-volatile memory element (NVM) material that individually extends past a plurality of crossings of the first and second conductive lines.

### Claim 2 (depends on 1)

The memory of claim 1, wherein
the third conductive lines are elongated in the y-direction,
the select devices are arranged to make those of the first conductive lines aligned in the y-direction connectable with selected ones of the plurality of third conductive lines, and
a plurality of control lines extending in the x-direction and individually connected with a plurality of the select devices aligned in the x-direction to enable connection of a plurality of first conductive lines aligned in the x-direction with different ones of the third conductive lines.

### Claim 3 (depends on 1)

The memory of either one of claim 1, wherein the plurality of select devices and the plurality of third conductive lines are formed in a semiconductor substrate and the plurality of planes are formed as a stack over the semiconductor substrate.

### Claim 4 (depends on 3)

The memory of claim 3, wherein the individual memory elements are characterized by including a material that reversibly changes its level of electrical conductance between at least first and second stable levels in response to an electrical stimulus being applied through the first and second conductive lines between which the memory element is connected.

### Claim 5 (depends on 1)

The memory of claim 1, wherein the individual memory elements are characterized by including a material that reversibly changes its level of electrical conductance between at least first and second stable levels in response to an electrical stimulus being applied through the first and second conductive lines between which the memory element is connected.

### Claim 6 (depends on 1)

The memory of claim 1, wherein the memory elements include a metal oxide.

### Claim 7 (depends on 6)

The memory of claim 6, wherein the metal oxide includes hafnium oxide.

### Claim 8 (depends on 1)

The memory of claim 1, wherein the memory elements are positioned on one side of the second conductive lines in the z-direction.

### Claim 9 (depends on 8)

The memory of claim 8, wherein the memory elements include at least one of a carbon material or a phase change material.

### Claim 10 (depends on 8)

The memory of claim 8, wherein memory elements include individual quantities of material adjacent individual ones of the crossings of the first and second conductive lines, the memory elements being separated from one another in all of the x, y and z-directions.

### Claim 11 (depends on 10)

The memory of claim 10, wherein the material of the memory elements is characterized by being electrically conductive.

### Claim 12 (depends on 10)

The memory of claim 10, wherein the memory elements are additionally positioned to contact the first conductive lines in the y-direction.

### Claim 13 (depends on 10)

The memory of claim 10, wherein the memory elements are additionally positioned on one side of individual conductive stubs in the z-direction, the individual conductive stubs being positioned to contact one of the first conductive lines in the y-direction.

### Claim 14 (depends on 1)

The memory of claim 1, wherein the individual memory elements are characterized by a level of electrical conductance that changes in response to an electrical stimulus applied thereto.

### Claim 15 (depends on 1)

The memory of claim 1, wherein the memory elements are characterized by having at least first and second stable electrically detectable states that are selected by electrical stimuli applied thereto through the first and second conductive lines.

### Claim 16 (depends on 15)

The memory of claim 15, additionally comprising a circuit connected to the first and second conductive lines to apply the electrical stimuli to selected ones of the memory elements, the electrical stimuli being applied to cause the selected memory elements to switch from their first to second stable states having substantially the same magnitude but different polarities as the electrical stimuli applied to cause the memory elements to switch from their second to first stable states.

### Claim 17 (depends on 1)

The memory of claim 1, wherein no diodes are connected in series with the memory elements between the first and second conductive lines.

### Claim 18 (depends on 1)

The memory of claim 1, additionally comprising data input-output circuits connected to the third plurality of conductive lines.

### Claim 19 (depends on 18)

The memory of claim 18, wherein the data input-output circuits include a plurality of sense amplifiers that are connected with the third conductive lines in a manner to provide a binary representation of data carried by the third conductive lines when data are being read from the memory.

### Claim 20 (depends on 18)

The memory of claim 18, wherein the data input-output circuits additionally include data programming circuits that apply voltages to the third conductive lines for programming data into at least some of the memory elements connected thereto through the plurality of select devices.