# US 2014/0192594 A1 · P-channel 3d memory array

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- Number: US 2014/0192594 A1
- Document ID: US20140192594A1
- Status: Published application
- Kind: A1
- Application number: 14/019,183
- Filed: 2013-09-05
- Published: 2014-07-10
- Earliest claimed: 2013-01-09
- Assignees: Macronix International Co., Ltd.
- Applicants: Macronix International Co., Ltd.
- Inventors: Hang-Ting Lue
- Web page: https://patentgrep.com/patent/US20140192594A1

## CPC

- G11C 16/0475: {comprising two or more independent storage sites which store independent data}
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/10: Programming or data input circuits
- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/35: with cell select transistors, e.g. NAND
- G11C 2213/71: Three dimensional array
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A p-channel flash memory device including a 3D NAND array has excellent performance characteristics. Techniques for operating 3D, p-channel NAND arrays include selective programming, selective (bit) erase, and block erase. Selective programming bias arrangements induce band-to-band tunneling current hot electron injection to increase threshold voltages in selected cells. Selective erase biasing arrangements induce −FN hole tunneling to decrease threshold voltages in selected cells. Also, block erase bias arrangements induce −FN hole tunneling in selected blocks of cells.

## Claims

### Claim 1

A method for operating a 3D, p-channel flash memory, comprising:
programming selected memory cells using band-to-band tunneling hot electron injection.

### Claim 2 (depends on 1)

The method of claim 1, including erasing selected blocks of cells using Fowler-Nordheim FN hole tunneling.

### Claim 3 (depends on 2)

The method of claim 2, including inhibiting erasing in unselected memory cells by local self-boosting.

### Claim 4 (depends on 1)

The method of claim 1, including erasing selected memory cells using FN hole tunneling, while inhibiting erasing of unselected memory cells.

### Claim 5 (depends on 1)

The method of claim 1, wherein said programming includes applying a positive program voltage to word lines of selected memory cells, and applying negative pass voltages to word lines of unselected memory cells.

### Claim 6 (depends on 1)

The method of claim 1, wherein said programming includes applying a positive program voltage to word lines of selected memory cells, and applying a negative drain side pass voltage to word lines of unselected memory cells on one side (drain side) of the selected memory cell, and a negative source side pass voltage to word lines of unselected memory cells on another side (source side) of the selected memory cell.

### Claim 7 (depends on 5)

The method of claim 5, wherein the positive program voltage has an absolute value magnitude less than 15V.

### Claim 8 (depends on 5)

The method of claim 5, including applying a non-negative voltage to bit lines of unselected memory cells.

### Claim 9

A method for operating a p-channel, dual gate flash memory, comprising:
programming selected memory cells using band-to-band tunneling hot electron injection.

### Claim 10

A method for operating a p-channel, dual gate flash memory, comprising:
erasing selected memory cells using negative Fowler-Nordheim tunneling of holes.

### Claim 11

A method for inducing hot electron injection in a selected memory cell in a p-channel NAND string in a NAND array, comprising:
applying a program bias arrangement to program a selected memory cell, the program bias arrangement including:
a positive program voltage pulse on a word line coupled with a selected memory cell, blocking flow of carriers between a first semiconductor body region on a first side of the selected memory cell and a second semiconductor body region on a second side of the selected memory cell;
a negative drain side pass voltage pulse on word lines in the plurality of word lines on the first side of the selected memory cell;
a negative source side pass voltage on word lines in the plurality of word lines on the second side of the selected memory cell; and
bias voltages to block current flow between a selected bit line and the semiconductor body region on the first side of the selected memory cell during the negative drain side pass voltage pulse thereby causing capacitive boosting of the first semiconductor region to a boosted, negative voltage level, and to allow current flow between a source line and the semiconductor body region on the second side of the selected memory cell thereby coupling the semiconductor body on the second side of the selected memory cell to the source line.

### Claim 12 (depends on 11)

The method of claim 11, wherein NAND strings in the NAND array include a first switch between a first end of the NAND string and a bit line or reference line and a second switch between a second end of the NAND string and a bit line or reference line, and wherein:
the bias voltages to block current flow between a selected bit line and the semiconductor body region on the first side of the selected memory cell include voltages which turn off the first switch in the NAND string including the selected memory cell; and
the bias voltages to allow current flow between the source line and the semiconductor body region on the second side of the selected cells include voltages which turn on the second switch and apply a reference voltage to the source line.

### Claim 13 (depends on 11)

The method of claim 11, wherein the NAND array comprises a 3D array.

### Claim 14 (depends on 11)

The method of claim 11, wherein the program bias arrangement includes bias voltages to prevent capacitive boosting in unselected NAND strings during the negative drain side pass voltage pulse.

### Claim 15

A memory comprising:
a 3D NAND array including a plurality of NAND strings, a NAND string in the array including a plurality of p-channel memory cells arranged in series in an n-type semiconductor body;
a plurality of word lines, word lines in the plurality coupled to corresponding memory cells in the plurality of memory cells; and
control circuitry coupled to the plurality of word lines adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line using a program bias arrangement that induces band-to-band tunneling hot electron injection.

### Claim 16 (depends on 15)

The memory of claim 15, wherein the program bias arrangement includes:
a positive program voltage pulse on a word line coupled with a selected memory cell, blocking flow of carriers between a first semiconductor body region on a first side of the selected memory cell and a second semiconductor body region on a second side of the selected memory cell;
a negative drain side pass voltage pulse on word lines in the plurality of word lines on the first side of the selected memory cell;
a negative source side pass voltage on word lines in the plurality of word lines on the second side of the selected memory cell; and
bias voltages to block current flow between a selected bit line and the semiconductor body region on the first side of the selected memory cell during the negative drain side pass voltage pulse thereby causing capacitive boosting of the first semiconductor region to a boosted, negative voltage level, and to allow current flow between a source line and the semiconductor body region on the second side of the selected memory cell thereby coupling the semiconductor body on the second side of the selected memory cell to the source line.

### Claim 17 (depends on 15)

The memory of claim 15, wherein the control circuitry is adapted for erasing a selected memory cell in the plurality of memory cells using a selective erase bias arrangement.

### Claim 18 (depends on 17)

The memory of claim 17, wherein the selective erase bias arrangement includes:
a negative erase voltage pulse on a word line coupled with a selected memory cell;
a negative drain side voltage pulse on unselected word lines in the plurality of word lines, the negative drain side pass voltage having an absolute magnitude less than the negative erase voltage pulse;
bias voltages to allow current flow between a selected bit line and the NAND string including the selected memory cell during the negative erase voltage pulse, and to allow current flow between a source line and the NAND string including the selected memory cell; and
bias voltages to block current flow between unselected bit lines and NAND strings not including the selected memory cell during the negative erase voltage pulse, and to block current flow between a source line and NAND strings not including the selected memory cell during the negative erase voltage pulse.

### Claim 19 (depends on 15)

The memory of claim 15, wherein the control circuitry is adapted for a block erase by a block erase bias arrangement to induce −FN hole tunneling.

### Claim 20 (depends on 15)

The memory of claim 15, wherein the memory cells comprise dual gate, thin film flash memory cells.

### Claim 21

A memory comprising:
a 3D NAND array including a plurality of NAND strings, a NAND string in the array including a plurality of p-channel memory cells arranged in series in an n-type semiconductor body;
a plurality of word lines, word lines in the plurality coupled to corresponding memory cells in the plurality of memory cells; and
control circuitry coupled to the plurality of word lines adapted for selectively erasing a selected memory cell in the plurality of memory cells using a selective erase bias arrangement to reduce a threshold in the selected memory cell.

### Claim 22 (depends on 21)

The memory of claim 21, wherein the selective erase bias arrangement includes:
a negative erase voltage pulse on a word line coupled with a selected memory cell;
a negative drain side voltage pulse on unselected word lines in the plurality of word lines, the negative drain side pass voltage having an absolute magnitude less than the negative erase voltage pulse;
bias voltages to allow current flow between a selected bit line and the NAND string including the selected memory cell during the negative erase voltage pulse, and to allow current flow between a source line and the NAND string including the selected memory cell; and
bias voltages to block current flow between unselected bit lines and NAND strings not including the selected memory cell during the negative erase voltage pulse, and to block current flow between a source line and NAND strings not including the selected memory cell during the negative erase voltage pulse.

### Claim 23 (depends on 21)

The memory of claim 21, wherein the selective erase bias arrangement induces −FN hole tunneling in the selected cell.

### Claim 24 (depends on 21)

The memory of claim 21, wherein the control circuitry is adapted for selectively programming a selected memory cell in the plurality of memory cells using a program bias arrangement to increase a threshold in the selected memory cell.

### Claim 25 (depends on 24)

The memory of claim 24, wherein the program bias arrangement induces band-to-band tunneling current hot electron injection.

### Claim 26

A memory comprising:
a NAND string including a plurality of p-channel dual gate flash memory cells in an n-type semiconductor body; and
control circuitry adapted for selectively erasing a selected memory cell in the plurality of memory cells using a selective erase bias arrangement, and for selectively programming a selected memory cell in the plurality of memory cells using a selective program bias arrangement.