# US 2014/0192593 A1 · Flash multi-level threshold distribution scheme

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- Number: US 2014/0192593 A1
- Document ID: US20140192593A1
- Status: Published application
- Kind: A1
- Application number: 14/208,812
- Filed: 2014-03-13
- Published: 2014-07-10
- Earliest claimed: 2006-09-13
- Assignees: Mosaid Technologies Incorporated
- Applicants: Mosaid Technologies Incorporated
- Inventors: Jin-Ki KIM
- Web page: https://patentgrep.com/patent/US20140192593A1

## CPC

- G11C 16/34: Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/10: Programming or data input circuits
- G11C 16/12: Programming voltage switching circuits
- G11C 16/344: {Arrangements for verifying correct erasure or for detecting overerased cells}
- G11C 16/3454: {Arrangements for verifying correct programming or for detecting overprogrammed cells}
- G11C 2211/5621: Multilevel programming verification
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages.

## Claims

### Claim 1

A NAND Flash memory device comprising:
a memory array having memory cells arranged in rows and columns, the memory array having a plurality of blocks and block erasable, each memory cell erasable to have an erase threshold voltage in an erase voltage domain and programmable to have a program threshold voltage in the erase voltage domain and a program voltage domain;
each memory cell being programmable to store two bits of data corresponding to first, second, third and fourth threshold voltages with the first threshold voltage and the second threshold voltage in the erase voltage domain, and the third threshold voltage and the fourth threshold voltage in the program voltage domain;
row control logic circuitry (100) for selectively driving a wordline connected to a gate terminal of a memory cell with one of a positive voltage and a negative voltage during program verify and read operations; and
a positive voltage generator (104) for providing a positive voltage, and a negative voltage generator (106) for providing a negative voltage, the erase voltage domain including threshold voltages that are negative and the program voltage domain includes threshold voltages that are positive, wherein the first threshold voltage corresponding to the erase threshold voltage.

### Claim 2 (depends on 1)

The NAND Flash memory device of claim 1, wherein the row control logic circuitry comprises:
a row decoder (108) for receiving the positive voltage and the negative voltage, the row decoder providing row signals in response to a row address; and
a wordline driver (110) for passing the row signals in response to an enable signal.

### Claim 3 (depends on 2)

The NAND Flash memory device of claim 2, wherein the row control logic circuitry further comprises:
a block decoder (102) for providing the enable signal in response to a block address, the enable signal having one of the positive voltage and the negative voltage.