# US 2014/0192591 A1 · High capacity low cost multi-state magnetic memory

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- Number: US 2014/0192591 A1
- Document ID: US20140192591A1
- Status: Published application
- Kind: A1
- Application number: 14/212,970
- Filed: 2014-03-14
- Published: 2014-07-10
- Earliest claimed: 2006-02-25
- Assignees: Avalanche Technology, Inc.
- Inventors: Parviz Keshtbod
- Web page: https://patentgrep.com/patent/US20140192591A1

## CPC

- G11C 11/1675: {Writing or programming circuits or methods}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- G11C 11/16: using elements in which the storage effect is based on magnetic spin effect
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 11/5607: {using magnetic storage elements}
- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10N 50/10: Magnetoresistive devices
- G11C 2211/5615: Multilevel magnetic memory cell using non-magnetic non-conducting interlayer, e.g. MTJ
- G11C: STATIC STORES (semiconductor memory devices H10B)
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states.

## Claims

### Claim 1

A method of writing to a magnetic memory cell comprising:
setting a first switch and a second switch, the first and second switches coupled to a magnetic memory cell, the magnetic memory cell including a first and a second magnetic memory elements coupled to each other in series, the setting of the first and second switches causing the first and second magnetic elements to switch states defining a state of the magnetic memory cell;
programming the magnetic memory cell to an intermediate state by setting one or both of the first and second switches; and
programming the magnetic memory cell by setting one or both of the first and second switches to a final state after programming it to the intermediate state.

### Claim 2 (depends on 1)

The method of claim 1, wherein the intermediate state is based on the final state.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first magnetic memory element has an aspect ratio that is less than an aspect ratio of the second magnetic memory element.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first and second switches cause different current levels to flow through the magnetic memory cell.

### Claim 5 (depends on 4)

The method of claim 4, wherein the first and second switches cause the different current levels to flow in different direction.

### Claim 6 (depends on 4)

The method of claim 4, wherein the current levels of the different current levels are substantially different to cause the resistance of the magnetic memory cell to change adequately to distinguish between two different states.

### Claim 7 (depends on 4)

The method of claim 4, wherein the different current levels are based, at least in part, on the resistances of the first and second magnetic memory elements.

### Claim 8 (depends on 4)

The method of claim 4, wherein the different current levels are for two current levels.

### Claim 9

The method of claim, further including sensing the state of the magnetic memory cell before the programming to the final state and based on the sensing, selectively skipping the intermediate state.

### Claim 10 (depends on 1)

The method of claim 1, wherein the first magnetic memory element has a first resistance and the second magnetic memory element has a second resistance, wherein the first resistance that is greater than the second resistance requiring the programming of the second magnetic memory element before the programming of the first magnetic memory element.

### Claim 11

A write circuit for programming a magnetic memory cell including more than one magnetic memory element comprising:
a first switch and a second switch;
a magnetic memory cell including a first magnetic memory element and a second magnetic memory element, the magnetic memory cell coupled to the first and second switches;
a first circuit coupled to the first switch;
a second circuit coupled to the first switch, the magnetic memory cell being at a state based on the position of the first and second switches, the writing circuit operable to:
program the magnetic memory cell to an intermediate state by setting one or both of the first and second switches; and
program the magnetic memory cell by setting one or both of the first and second switches to a final state after programming the magnetic memory cell to the intermediate state.

### Claim 12 (depends on 11)

The write circuit of claim 11, wherein the first circuit includes at least two transistors and one of the at least one transistors is larger than another of the at least two transistors.

### Claim 13 (depends on 11)

The write circuit of claim 11, wherein the second circuit includes at least two transistors and one of the at least one transistors is larger than another of the at least two transistors.

### Claim 14 (depends on 11)

The write circuit of claim 11, further including a first current source coupled to the first circuit.

### Claim 15 (depends on 11)

The write circuit of claim 11, further including a second current source coupled between the second circuit and the first circuit.

### Claim 16 (depends on 11)

The write circuit of claim 11, further including a third switch coupled between the first circuit and the first switch.

### Claim 17 (depends on 11)

The write circuit of claim 11, further including a fourth switch coupled between the second circuit and the first switch.