# US 2014/0192590 A1 · Multi-port magnetic random access memory (mram)

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- Number: US 2014/0192590 A1
- Document ID: US20140192590A1
- Status: Published application
- Kind: A1
- Application number: 14/204,274
- Filed: 2014-03-11
- Published: 2014-07-10
- Earliest claimed: 2012-08-14
- Assignees: Avalanche Technology, Inc.
- Inventors: Ebrahim Abedifard; Parviz Keshtbod
- Web page: https://patentgrep.com/patent/US20140192590A1

## CPC

- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 8/16: Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
- G11C 11/16: using elements in which the storage effect is based on magnetic spin effect
- G11C 11/1657: {Word-line or row circuits}
- G11C 11/1659: {Cell access}
- G11C 11/1675: {Writing or programming circuits or methods}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line. The memory array further has other resistive elements that are each coupled to the bit line. The resistive element is written to while one or more of the other resistive elements are being read.

## Claims

### Claim 1

A memory array organized into rows and columns of resistive elements, the memory array comprising:
a resistive element to be read or to be written thereto;
a first access transistor coupled to the resistive element, to a first source line, and to a first word line; and
a second access transistor coupled to the resistive element, a second source line, and to a second word line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line;
wherein the resistive element is read through the first word line and the second word line at substantially the same time.

### Claim 2 (depends on 1)

The memory array of claim 1, wherein the resistive element is written to while one or more other resistive elements, coupled to another bit line, are read.

### Claim 3 (depends on 1)

The memory array, as recited in claim 1, wherein the resistive element is a magnetic random access memory (MRAM).

### Claim 4 (depends on 1)

The memory array, as recited in claim 1, wherein the resistive element is a magnetic tunnel junction (MTJ).

### Claim 5 (depends on 1)

The memory array, as recited in claim 1, wherein the first and second access transistors each have a gate and the gate of each of the first and second access transistors is coupled to a distinct word line.

### Claim 5 (depends on 1)

The memory array, as recited in claim 1, wherein at least some of the other resistive elements of the memory array is coupled to a pair of first and second access transistors with each of the first access transistors of each of the pairs being coupled to first sense line and each of the second access transistors of each of the pairs being coupled to second sense line.

### Claim 7 (depends on 1)

The memory array, as recited in claim 1, wherein each of the first and second access transistors of the pair has a gate that is coupled to a distinct word line.

### Claim 8 (depends on 1)

The memory array, as recited in claim 1, further including a third access transistor coupled to the resistive element and to the second sense line, the third access transistor having a gate that is coupled to a word line that is distinct from the word lines to which the first and second access transistors are coupled.

### Claim 9 (depends on 1)

The memory array, as recited in claim 1, wherein the resistive element is read while one or more other resistive elements coupled to another bit line are written thereto.

### Claim 10

A method of reading from and writing to resistive elements of a memory array organized into rows and columns of resistive elements, the method comprising:
accessing a first resistive element through at least a first access transistor, the first access transistor coupled to the resistive element, a first source line, and a first word line, a second access transistor coupled to the resistive element, a second source line, and a second word line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line; and
reading the resistive element through the first word line and the second word line at substantially the same time.