# US 2014/0192589 A1 · Reduced diffusion in metal electrode for two-terminal memory

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- Number: US 2014/0192589 A1
- Document ID: US20140192589A1
- Status: Published application
- Kind: A1
- Application number: 14/207,430
- Filed: 2014-03-12
- Published: 2014-07-10
- Earliest claimed: 2012-04-13
- Assignees: Crossbar, Inc.
- Applicants: Crossbar, Inc.
- Inventors: Steven Patrick MAXWELL; Sung-Hyun JO
- Web page: https://patentgrep.com/patent/US20140192589A1

## CPC

- H10N 70/8416: {adapted for supplying ionic species}
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C 13/0011: {comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/0028: {Word-line or row circuits}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/021: {Formation of switching materials, e.g. deposition of layers}
- H10N 70/245: {the species being metal cations, e.g. programmable metallization cells}
- H10N 70/801: {Constructional details of multistable switching devices}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8822: {Sulfides, e.g. CuS}
- H10N 70/8825: {Selenides, e.g. GeSe}
- H10N 70/883: {Oxides or nitrides}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10N 70/884: {based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors (compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883)}
- G11C 2213/51: Structure including a barrier layer preventing or limiting migration, diffusion of ions or charges or formation of electrolytes near an electrode
- G11C 2213/52: Structure characterized by the electrode material, shape, etc.
- G11C 2213/56: Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way
- G11C 2213/77: Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Providing for two-terminal memory that mitigates diffusion of external material therein is described herein. In some embodiments, a two-terminal memory cell can comprise an electrode layer. The electrode layer can be at least in part permeable to ionically or chemically reactive material, such as oxygen or the like. The two-terminal memory can further comprise a diffusion mitigation material disposed between the electrode layer and external material. This diffusion mitigation material can be selected to mitigate or prevent diffusion of the undesired element(s) or compound(s), to mitigate or avoid exposure of such element(s) or compound(s) to the electrode layer. Accordingly, degradation of the two-terminal memory as a result of contact with the undesired element(s) or compound(s) can be mitigated by various disclosed embodiments.

## Claims

### Claim 1

A memory cell arranged in a monolithic stack, comprising:
a bottom electrode comprising an electrically conductive material;
a switching medium comprising an electrically resistive material;
a top electrode comprising a noble metal that produces ions at a boundary of the top electrode and the switching medium in response to an electric field applied to the memory cell, wherein the switching medium is at least in part permeable to the ions; and
a passivation layer comprising a non-noble metal disposed at an opposite side of the top electrode from the switching medium, wherein the passivation layer reduces diffusion of one or more atmospheric gasses into the top electrode.

### Claim 2 (depends on 1)

The memory cell of claim 1, wherein the passivation layer is in immediate contact with the top electrode.

### Claim 3 (depends on 1)

The memory cell of claim 1, wherein the non-noble metal of the passivation layer is selected from a group consisting of: W, tungsten nitride, Ti, TiW, Al, Cu and TiN.

### Claim 4 (depends on 1)

The memory cell of claim 1, wherein the passivation layer is deposited above the top electrode in an oxygen-free environment.

### Claim 5 (depends on 4)

The memory cell of claim 4, wherein the passivation layer is deposited using a physical vapor deposition process.

### Claim 6 (depends on 4)

The memory cell of claim 4, wherein the passivation layer is deposited using a chemical vapor deposition process.

### Claim 7 (depends on 1)

The memory cell of claim 1, wherein the noble metal of the top electrode is Ag.

### Claim 8 (depends on 1)

The memory cell of claim 1, wherein the electrically conductive material of the bottom electrode comprises a conductive metal and a doped silicon material.

### Claim 9 (depends on 1)

The memory cell of claim 1, wherein the switching medium is comprised of an undoped amorphous Si, an amorphous compound of Si, or a Si sub-oxide.

### Claim 10 (depends on 1)

The memory cell of claim 1, wherein the passivation layer has a thickness in a range of about 10 nanometers (nm) and about 50 nm.

### Claim 11 (depends on 1)

The memory cell of claim 1, further comprising a barrier layer disposed between the switching medium and the top electrode selected from a group consisting of: Ti, TiN and TiO.

### Claim 12 (depends on 11)

The memory cell of claim 11, wherein the barrier layer has a thickness of about 3 nm to about 10 nm.

### Claim 13 (depends on 1)

The memory cell of claim 1, further comprising:
a semiconductor substrate upon which the memory cell is disposed, the semiconductor substrate comprising at least one complementary metal oxide semiconductor device;
a first metal conductor built on the semiconductor substrate and in electrical contact with the bottom electrode; and
a second metal conductor formed at least in part as a metal hardmask in contact with the passivation layer, wherein the first metal wire and the second metal wire facilitate application of a signal to the memory cell.

### Claim 14

A method of fabricating a memory cell, comprising:
forming a first electrically conductive electrode layer above a substrate material;
forming an electrically resistive switching medium above the first conductive electrode layer that is permeable to ions of at least one noble metal;
forming a second electrically conductive electrode layer comprising the at least one noble metal above the electrically resistive switching medium; and
forming a diffusion mitigation layer comprising a non-noble metal above the second electrically conductive electrode layer; and
wherein: the second electrically conductive electrode layer is configured to generate ions at least at a surface closest to the electrically resistive switching medium in response to an electric field,
wherein the fabricating is performed in a reduced oxygen environment, and
wherein the non-noble metal is configured to mitigate exposure of the second electrically conductive electrode layer to oxygen.

### Claim 15 (depends on 14)

The method of claim 14, further comprising selecting for the non-noble metal of the diffusion mitigation layer is selected from a group consisting of W, Ti, TiN, Al, Cu, WN, and TiW.

### Claim 16 (depends on 14)

The method of claim 14, wherein the forming the diffusion mitigation layer is performed within a amount of time after the forming the electrically resistive switching layer, wherein the amount of time is within a range of about 1 hour to about 8 hours.

### Claim 17 (depends on 14)

The method of claim 14, further comprising forming a barrier layer that is selected from a group consisting of: Ti, TiN and TiO disposed between the electrically resistive switching medium and the second electrically conductive electrode layer, wherein the barrier layer has a thickness about 10 nanometers (nm) or less, and the diffusion mitigation layer has a thickness within a range of about 10 nm to about 50 nm.

### Claim 18

An electronic device, comprising:
an array of memory cells comprising a substrate having a complementary semiconductor metal oxide device and a two-terminal memory cell, both formed at least in part on or above the substrate, wherein the memory is configured to store instructions related to operating the electronic device;
a command interface configured to receive an instruction pertaining to performing a memory operation with respect to the array of memory cells; and
a controller configured to execute the memory operation on the at least one two-terminal memory cell via one or more signal inputs in response to receipt of the instruction at the command interface and processing of the command, wherein the two-terminal memory cell further comprises:
a bottom electrode, a switching medium, a top electrode comprising a noble metal and a passivation layer comprising a non-noble metal in immediate contact with the top electrode, wherein the passivation layer is configured to mitigate exposure of the top electrode to oxygen.

### Claim 19 (depends on 18)

The electronic device of claim 18, wherein:
the noble metal of the top electrode is one of Ag, Pt or Pd; and
the non-noble metal of the passivation layer is one of W, Ti, TiN, Al, Cu, WN, or TiW.

### Claim 20 (depends on 18)

The electronic device of claim 18, wherein the passivation layer has a thickness in a range of about 10 nanometers (nm) to about 50 nm.