# US 2014/0192588 A1 · Nonvolatile Memory Device and Read Method Thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0192588 A1 - Document ID: US20140192588A1 - Status: Published application - Kind: A1 - Application number: 14/146,748 - Filed: 2014-01-03 - Published: 2014-07-10 - Earliest claimed: 2013-01-10 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Sungyeon Lee; Yeongtaek Lee; Kiwon Lim; Wonryul Chung - Web page: https://patentgrep.com/patent/US20140192588A1 ## CPC - G11C 13/004: {Reading or sensing circuits or methods} - G11C 11/5678: {using amorphous/crystalline phase transition storage elements} - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 13/0069: {Writing or programming circuits or methods} - G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell} - G11C 2213/71: Three dimensional array - G11C 2213/72: Array wherein the access device being a diode - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A nonvolatile memory device is provided which includes a main area including main cells connected to word lines and main bit lines; a reference area including reference cells connected to the word lines and reference bit lines and programmed using the same write condition as that of the main area; a reference sense amplifier circuit configured to read data written at the reference area through the reference bit lines at a read operation; and control logic configured to control the reference sense amplifier circuit such that data written at the reference area is shifted with a weight scheme and then read, the data written at the reference area being used as a read reference value of the main area at a read operation. ## Claims ### Claim 1 A nonvolatile memory device, comprising: a main area including main cells connected to word lines and main bit lines; a reference area including reference cells connected to the word lines and reference bit lines and programmed using a same write condition as that of the main area; and control logic configured to cause data written at the reference area is shifted with a weighting scheme and then read, the data written at the reference area being used as a read reference value of the main area at a read operation. ### Claim 2 (depends on 1) The nonvolatile memory device of claim 1, further comprising a reference sense amplifier circuit configured to read data written at the reference area through the reference bit lines at a read operation. ### Claim 3 (depends on 2) The nonvolatile memory device of claim 2, wherein the reference area is programmed using a same verification voltage as that of the main area, ### Claim 4 (depends on 2) The nonvolatile memory device of claim 2, wherein the reference area is programmed at a same time as the main area. ### Claim 5 (depends on 2) The nonvolatile memory device of claim 2, wherein the control logic is configured to adjust a level of a compensation current provided to the reference sense amplifier circuit and to control the reference sense amplifier circuit such that data written at the reference area is read with the weighting scheme. ### Claim 6 (depends on 2) The nonvolatile memory device of claim 2, wherein the control logic is configured to adjust a level of a clamp voltage provided to the reference sense amplifier circuit and to control the reference sense amplifier circuit such that data written at the reference area is read with the weighting scheme. ### Claim 7 A nonvolatile memory device, comprising: a main area including a first main cell programmed to have a first resistance level corresponding to first data and a second main cell programmed to have a second resistance level corresponding to second data; a reference area including a reference cell programmed to have the first resistance level; a reference sense amplifier circuit configured to read a resistance value of the reference cell under a first read condition at a read operation and to generate a reference voltage based on the resistance value of the reference cell read; and a main sense amplifier circuit configured to read data stored at the first and second main cells using the reference voltage under a second read condition that is different from the first read condition, wherein the first and second main cells and the reference cell share a same word line. ### Claim 8 (depends on 7) The nonvolatile memory device of claim 7, wherein the resistance value of the reference cell read has a value between resistance values of the first and second main cells. ### Claim 9 (depends on 8) The nonvolatile memory device of claim 8, wherein the resistance value of the reference cell read under the first read condition is shifted with a weight that is varied in response to a size of the first resistance level and the shifted resistance value is then read. ### Claim 10 (depends on 9) The nonvolatile memory device of claim 9, wherein the weight is varied according to a time elapsing from a program operation on the reference cell. ### Claim 12 (depends on 10) The nonvolatile memory device of claim 10, wherein the resistance value of the reference cell read under the first read condition is shifted over a margin and the shifted resistance value is then read. ### Claim 12 A read method of a nonvolatile memory device including a main area including main cells connected to word lines and main bit lines; and a reference area including reference cells connected to the word lines and reference bit lines and programmed using a same write condition as that of the main area, the read method comprising: shifting data stored at the reference area with a weighting scheme to read the shifted data; generating a reference voltage based on the read data; and reading data stored at the main area using the reference voltage. ### Claim 13 (depends on 12) The read method of claim 12, wherein the reference area is programmed using a same verification voltage as that of the main area. ### Claim 14 (depends on 13) The read method of claim 13, wherein the reference area is programmed at a same time with the main area. ### Claim 15 (depends on 12) The read method of claim 12, wherein a weight applied to shift data stored at the reference area is varied according to a time elapsing from a program operation on the reference cell. ### Claim 16 (depends on 13) The read method of claim 13, wherein the weight is varied in response to data stored at the reference area.