# US 2014/0192585 A1 · Resistive Random Access Memory Cell Having Three or More Resistive States

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- Number: US 2014/0192585 A1
- Document ID: US20140192585A1
- Status: Published application
- Kind: A1
- Application number: 13/738,061
- Filed: 2013-01-10
- Published: 2014-07-10
- Earliest claimed: 2013-01-10
- Assignees: Intermolecular, Inc.; SanDisk 3D LLC; Kabushiki Kaisha Toshiba
- Applicants: Intermolecular Inc.; Kabushiki Kaisha Toshiba; Sandisk 3D LLC
- Inventors: Imran Hashim; Ryan C. Clarke; Nan Lu; Tim Minvielle; Takeshi Yamaguchi
- Web page: https://patentgrep.com/patent/US20140192585A1

## CPC

- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C 11/5685: {using storage elements comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0064: {Verifying circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 13/0097: {Erasing, e.g. resetting, circuits or methods}
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/841: {Electrodes}
- G11C 2213/32: Material having simple binary metal oxide structure
- G11C 2213/71: Three dimensional array
- G11C 2213/77: Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Provided are resistive random access memory (ReRAM) cells, each having three or more resistive states and being capable of storing multiple bits of data, as well as methods of fabricating and operating such ReRAM cells. Such ReRAM cells or, more specifically, their resistive switching layer have wide range of resistive states and are capable of being very conductive (e.g., about 1 kOhm) in one state and very resistive (e.g., about 1 MOhm) in another state. In some embodiments, a resistance ratio between resistive states may be between 10 and 1,000 even up to 10,000. The resistive switching layers also allow establishing stable and distinct intermediate resistive states that may be assigned different data values. These layers may be configured to switching between their resistive states using fewer programming pulses than conventional systems by using specific materials, switching pluses, and resistive state threshold.

## Claims

### Claim 1

A method of switching a resistive random access memory (ReRAM) cell among three or more resistive states, the method comprising:
providing the ReRAM cell comprising a resistive switching layer,
the resistive switching layer comprising one of hafnium oxide, zirconium oxide, silicon oxide, or a combination of titanium oxide and aluminum oxide;
wherein the resistive switching layer has a first resistance; applying a first set of programming pulses to the ReRAM cell,
wherein, after applying the first set of programming pulses, the resistive switching layer has a second resistance less than the first resistance; and applying a second set of programming pulses to the ReRAM cell,
wherein, after applying the second set of programming pulses, the resistive switching layer has a third resistance less than the second resistance, and
wherein a ratio of the first resistance to the third resistance is between 10 and 1000.

### Claim 2 (depends on 1)

The method of claim 1, wherein the ratio of the first resistance to the third resistance is between 100 and 1000.

### Claim 3 (depends on 1)

The method of claim 1, wherein the ratio of the first resistance to the second resistance is between 5 and 1000.

### Claim 4 (depends on 3)

The method of claim 3, wherein the first set of programming pulses has less than three programming pulses.

### Claim 5 (depends on 1)

The method of claim 1, wherein a voltage of each programming pulse in the first set of programming pulses is increased by a predetermined value.

### Claim 6 (depends on 1)

The method of claim 1, wherein applying the first set of programming pulses further comprises applying a read pulse after each programming pulse, wherein the read pulse is used to determine a current resistive state of the ReRAM cell and determine whether an additional programming pulse is needed.

### Claim 7 (depends on 1)

The method of claim 1, wherein a ratio of the second resistance to the third resistance is between 5 and 1000.

### Claim 8 (depends on 1)

The method of claim 1, wherein the second set of programming pulses has less than three programming pulses.

### Claim 9 (depends on 1)

The method of claim 1, further comprising applying a third set of programming pulses to the ReRAM cell,
wherein, after applying the third set of programming pulses, the resistive switching layer has a fourth resistance less than the third resistance, and
wherein a ratio of the third resistance to the fourth resistance is between 5 and 1000.

### Claim 10 (depends on 1)

The method of claim 1, further comprising applying a set of erase pulses to the ReRAM cell,
wherein, after applying the set of erase pulses, the resistive switching layer has the first resistance.

### Claim 11 (depends on 10)

The method of claim 10, wherein the set of erase pulses includes less than four pulses.

### Claim 12 (depends on 10)

The method of claim 10, wherein applying the first set of erase pulses further comprises applying a read pulse after each programming pulse, wherein the read pulse is used to determine a current resistive state of the ReRAM cell and determine whether an additional erase pulse is needed.

### Claim 13 (depends on 1)

The method of claim 1, wherein applying the first set of programming pulses to the ReRAM cell comprises:
(a) applying a programming pulse;
(b) determining a present resistance of the resistive switching layer; and
(c) comparing the present resistance to a threshold resistance and repeating (a)-(c) if the present resistance is higher than the threshold resistance.

### Claim 14 (depends on 1)

The method of claim 1, wherein two sequential pulses in the first set of programming pulses have a voltage difference of between 0.1V and 0.3V.

### Claim 15 (depends on 1)

The method of claim 1, further comprising applying a set of forming pulses before applying the first set of programming pulses.

### Claim 16 (depends on 1)

The method of claim 1, wherein the resistive switching layer comprises a dopant, the dopant comprises one of titanium, hafnium, or aluminum.

### Claim 17 (depends on 1)

The method of claim 1, wherein the resistive switching layer comprises a first sub-layer, a second sub-layer, and a third sub-layer, and wherein the first sub-layer comprises titanium oxide, the second sub-layer comprises hafnium oxide, and the third sub-layer comprises silicon oxide.

### Claim 18 (depends on 17)

The method of claim 17, wherein the first sub-layer directly interfaces a first electrode, wherein the third sub-layer directly interfaces a second electrode, and wherein the second sub-layer is disposed between the first sub-layer and the third sub-layer.

### Claim 19 (depends on 18)

The method of claim 18, wherein the first electrode comprises titanium nitride, and wherein the second electrode comprises n-doped polysilicon.

### Claim 20

A resistive random access memory cell comprising:
a first electrode layer comprising an oxygen reactive material;
a second electrode layer comprising an oxygen inert material; and
a resistive switching layer comprising one of hafnium oxide, zirconium oxide, silicon oxide, or a combination of titanium oxide and aluminum oxide,
the resistive switching layer capable of being switched among four or more different resistive states,
wherein a ratio of resistances in at least two of the four or more different resistive states is between 10 and 1000.